Position-based rendering apparatus and method for multi-die/GPU graphics processing

ABSTRACT

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

BACKGROUND Field of the Invention

This invention relates generally to the field of graphics processors.More particularly, the invention relates to an apparatus and method forposition-based rendering on a multi-die or multiple-GPU graphicsprocessing.

Description of the Related Art

As graphics processors scale to larger die sizes, it is desirable tointegrate multiple silicon dies into a single cohesive unit capable ofrunning a single 3D context in order to address manufacturability,scalability, and power delivery problems. Doing this requires solutionsfor multiple classes of scalability and interconnect challenges in orderto deliver the best performance on a single 3D application running onmultiple dies.

Algorithms currently in use which attempt to address this probleminclude alternate frame rendering (AFR) and split frame rendering (SFR)as well as variants of these approaches.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained from thefollowing detailed description in conjunction with the followingdrawings, in which:

FIG. 1 is a block diagram of an embodiment of a computer system with aprocessor having one or more processor cores and graphics processors;

FIG. 2 is a block diagram of one embodiment of a processor having one ormore processor cores, an integrated memory controller, and an integratedgraphics processor;

FIG. 3 is a block diagram of one embodiment of a graphics processorwhich may be a discreet graphics processing unit, or may be graphicsprocessor integrated with a plurality of processing cores;

FIG. 4 is a block diagram of an embodiment of a graphics-processingengine for a graphics processor;

FIG. 5 is a block diagram of another embodiment of a graphics processor;

FIG. 6 is a block diagram of thread execution logic including an arrayof processing elements;

FIG. 7 illustrates a graphics processor execution unit instructionformat according to an embodiment;

FIG. 8 is a block diagram of another embodiment of a graphics processorwhich includes a graphics pipeline, a media pipeline, a display engine,thread execution logic, and a render output pipeline;

FIG. 9A is a block diagram illustrating a graphics processor commandformat according to an embodiment;

FIG. 9B is a block diagram illustrating a graphics processor commandsequence according to an embodiment;

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system according to an embodiment;

FIG. 11 illustrates an exemplary IP core development system that may beused to manufacture an integrated circuit to perform operationsaccording to an embodiment;

FIG. 12 illustrates an exemplary system on a chip integrated circuitthat may be fabricated using one or more IP cores, according to anembodiment;

FIG. 13 illustrates an exemplary graphics processor of a system on achip integrated circuit that may be fabricated using one or more IPcores;

FIG. 14 illustrates an additional exemplary graphics processor of asystem on a chip integrated circuit that may be fabricated using one ormore IP cores;

FIG. 15 is a block diagram illustrating a computer system configured toimplement one or more aspects of the embodiments described herein;

FIG. 16A-16D illustrate a parallel processor components, according to anembodiment;

FIGS. 17A-17B are block diagrams of graphics multiprocessors, accordingto embodiments;

FIG. 18A-18F illustrate an exemplary architecture in which a pluralityof GPUs are communicatively coupled to a plurality of multi-coreprocessors;

FIG. 19 illustrates a graphics processing pipeline, according to anembodiment;

FIG. 20 illustrates example results showing a percentage increase inperformance compared to execution on a single graphics processor;

FIG. 21 illustrates an example in which work partitioned across fourtiles is not evenly distributed;

FIG. 22 illustrates one embodiment of a method for performing positionsharing using checkerboard tiles;

FIG. 23 illustrates an example tile pattern to be processed by a set ofGPUs;

FIG. 24 illustrates an example allocation of position only shading workto generate visible vertex data; and

FIG. 25 illustrates an example allocation of tile-based shading work.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the embodiments of the invention described below. Itwill be apparent, however, to one skilled in the art that theembodiments of the invention may be practiced without some of thesespecific details. In other instances, well-known structures and devicesare shown in block diagram form to avoid obscuring the underlyingprinciples of the embodiments of the invention.

Exemplary Graphics Processor Architectures and Data Types

System Overview

FIG. 1 is a block diagram of a processing system 100, according to anembodiment. In various embodiments the system 100 includes one or moreprocessors 102 and one or more graphics processors 108, and may be asingle processor desktop system, a multiprocessor workstation system, ora server system having a large number of processors 102 or processorcores 107. In one embodiment, the system 100 is a processing platformincorporated within a system-on-a-chip (SoC) integrated circuit for usein mobile, handheld, or embedded devices.

An embodiment of system 100 can include, or be incorporated within aserver-based gaming platform, a game console, including a game and mediaconsole, a mobile gaming console, a handheld game console, or an onlinegame console. In some embodiments system 100 is a mobile phone, smartphone, tablet computing device or mobile Internet device. Dataprocessing system 100 can also include, couple with, or be integratedwithin a wearable device, such as a smart watch wearable device, smarteyewear device, augmented reality device, or virtual reality device. Insome embodiments, data processing system 100 is a television or set topbox device having one or more processors 102 and a graphical interfacegenerated by one or more graphics processors 108.

In some embodiments, the one or more processors 102 each include one ormore processor cores 107 to process instructions which, when executed,perform operations for system and user software. In some embodiments,each of the one or more processor cores 107 is configured to process aspecific instruction set 109. In some embodiments, instruction set 109may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). Multiple processor cores 107 may each process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 is additionally includedin processor 102 which may include different types of registers forstoring different types of data (e.g., integer registers, floating pointregisters, status registers, and an instruction pointer register). Someregisters may be general-purpose registers, while other registers may bespecific to the design of the processor 102.

In some embodiments, processor 102 is coupled with a processor bus 110to transmit communication signals such as address, data, or controlsignals between processor 102 and other components in system 100. In oneembodiment the system 100 uses an exemplary ‘hub’ system architecture,including a memory controller hub 116 and an Input Output (I/O)controller hub 130. A memory controller hub 116 facilitatescommunication between a memory device and other components of system100, while an I/O Controller Hub (ICH) 130 provides connections to I/Odevices via a local I/O bus. In one embodiment, the logic of the memorycontroller hub 116 is integrated within the processor.

Memory device 120 can be a dynamic random access memory (DRAM) device, astatic random access memory (SRAM) device, flash memory device,phase-change memory device, or some other memory device having suitableperformance to serve as process memory. In one embodiment the memorydevice 120 can operate as system memory for the system 100, to storedata 122 and instructions 121 for use when the one or more processors102 executes an application or process. Memory controller hub 116 alsocouples with an optional external graphics processor 112, which maycommunicate with the one or more graphics processors 108 in processors102 to perform graphics and media operations.

In some embodiments, ICH 130 enables peripherals to connect to memorydevice 120 and processor 102 via a high-speed I/O bus. The I/Operipherals include, but are not limited to, an audio controller 146, afirmware interface 128, a wireless transceiver 126 (e.g., Wi-Fi,Bluetooth), a data storage device 124 (e.g., hard disk drive, flashmemory, etc.), and a legacy I/O controller 140 for coupling legacy(e.g., Personal System 2 (PS/2)) devices to the system. One or moreUniversal Serial Bus (USB) controllers 142 connect input devices, suchas keyboard and mouse 144 combinations. A network controller 134 mayalso couple with ICH 130. In some embodiments, a high-performancenetwork controller (not shown) couples with processor bus 110. It willbe appreciated that the system 100 shown is exemplary and not limiting,as other types of data processing systems that are differentlyconfigured may also be used. For example, the I/O controller hub 130 maybe integrated within the one or more processor 102, or the memorycontroller hub 116 and I/O controller hub 130 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 112.

FIG. 2 is a block diagram of an embodiment of a processor 200 having oneor more processor cores 202A-202N, an integrated memory controller 214,and an integrated graphics processor 208. Those elements of FIG. 2having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Processor200 can include additional cores up to and including additional core202N represented by the dashed lined boxes. Each of processor cores202A-202N includes one or more internal cache units 204A-204N. In someembodiments each processor core also has access to one or more sharedcached units 206.

The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more Peripheral Component Interconnect buses (e.g., PCI, PCIExpress). System agent core 210 provides management functionality forthe various processor components. In some embodiments, system agent core210 includes one or more integrated memory controllers 214 to manageaccess to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, a displaycontroller 211 is coupled with the graphics processor 208 to drivegraphics processor output to one or more coupled displays. In someembodiments, display controller 211 may be a separate module coupledwith the graphics processor via at least one interconnect, or may beintegrated within the graphics processor 208 or system agent core 210.

In some embodiments, a ring based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect 212 via an I/O link213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202A-202N and graphicsprocessor 208 use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-202Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment processor cores 202A-202N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. Additionally, processor200 can be implemented on one or more chips or as an SoC integratedcircuit having the illustrated components, in addition to othercomponents.

FIG. 3 is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In some embodiments,the graphics processor communicates via a memory mapped I/O interface toregisters on the graphics processor and with commands placed into theprocessor memory. In some embodiments, graphics processor 300 includes amemory interface 314 to access memory. Memory interface 314 can be aninterface to local memory, one or more internal caches, one or moreshared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 320.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. In some embodiments, graphics processor 300 includesa video codec engine 306 to encode, decode, or transcode media to, from,or between one or more media encoding formats, including, but notlimited to Moving Picture Experts Group (MPEG) formats such as MPEG-2,Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well asthe Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1,and Joint Photographic Experts Group (JPEG) formats such as JPEG, andMotion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 310. In someembodiments, GPE 310 is a compute engine for performing graphicsoperations, including three-dimensional (3D) graphics operations andmedia operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

Graphics Processing Engine

FIG. 4 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the graphics processing engine (GPE) 410 is a version of theGPE 310 shown in FIG. 3. Elements of FIG. 4 having the same referencenumbers (or names) as the elements of any other figure herein canoperate or function in any manner similar to that described elsewhereherein, but are not limited to such. For example, the 3D pipeline 312and media pipeline 316 of FIG. 3 are illustrated. The media pipeline 316is optional in some embodiments of the GPE 410 and may not be explicitlyincluded within the GPE 410. For example and in at least one embodiment,a separate media and/or image processor is coupled to the GPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer403, which provides a command stream to the 3D pipeline 312 and/or mediapipelines 316. In some embodiments, command streamer 403 is coupled withmemory, which can be system memory, or one or more of internal cachememory and shared cache memory. In some embodiments, command streamer403 receives commands from the memory and sends the commands to 3Dpipeline 312 and/or media pipeline 316. The commands are directivesfetched from a ring buffer, which stores commands for the 3D pipeline312 and media pipeline 316. In one embodiment, the ring buffer canadditionally include batch command buffers storing batches of multiplecommands. The commands for the 3D pipeline 312 can also includereferences to data stored in memory, such as but not limited to vertexand geometry data for the 3D pipeline 312 and/or image data and memoryobjects for the media pipeline 316. The 3D pipeline 312 and mediapipeline 316 process the commands and data by performing operations vialogic within the respective pipelines or by dispatching one or moreexecution threads to a graphics core array 414.

In various embodiments the 3D pipeline 312 can execute one or moreshader programs, such as vertex shaders, geometry shaders, pixelshaders, fragment shaders, compute shaders, or other shader programs, byprocessing the instructions and dispatching execution threads to thegraphics core array 414. The graphics core array 414 provides a unifiedblock of execution resources. Multi-purpose execution logic (e.g.,execution units) within the graphic core array 414 includes support forvarious 3D API shader languages and can execute multiple simultaneousexecution threads associated with multiple shaders.

In some embodiments the graphics core array 414 also includes executionlogic to perform media functions, such as video and/or image processing.In one embodiment, the execution units additionally includegeneral-purpose logic that is programmable to perform parallel generalpurpose computational operations, in addition to graphics processingoperations. The general purpose logic can perform processing operationsin parallel or in conjunction with general purpose logic within theprocessor core(s) 107 of FIG. 1 or core 202A-202N as in FIG. 2.

Output data generated by threads executing on the graphics core array414 can output data to memory in a unified return buffer (URB) 418. TheURB 418 can store data for multiple threads. In some embodiments the URB418 may be used to send data between different threads executing on thegraphics core array 414. In some embodiments the URB 418 mayadditionally be used for synchronization between threads on the graphicscore array and fixed function logic within the shared function logic420.

In some embodiments, graphics core array 414 is scalable, such that thearray includes a variable number of graphics cores, each having avariable number of execution units based on the target power andperformance level of GPE 410. In one embodiment the execution resourcesare dynamically scalable, such that execution resources may be enabledor disabled as needed.

The graphics core array 414 couples with shared function logic 420 thatincludes multiple resources that are shared between the graphics coresin the graphics core array. The shared functions within the sharedfunction logic 420 are hardware logic units that provide specializedsupplemental functionality to the graphics core array 414. In variousembodiments, shared function logic 420 includes but is not limited tosampler 421, math 422, and inter-thread communication (ITC) 423 logic.Additionally, some embodiments implement one or more cache(s) 425 withinthe shared function logic 420. A shared function is implemented wherethe demand for a given specialized function is insufficient forinclusion within the graphics core array 414. Instead a singleinstantiation of that specialized function is implemented as astand-alone entity in the shared function logic 420 and shared among theexecution resources within the graphics core array 414. The precise setof functions that are shared between the graphics core array 414 andincluded within the graphics core array 414 varies between embodiments.

FIG. 5 is a block diagram of another embodiment of a graphics processor500. Elements of FIG. 5 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 500 includes a ring interconnect502, a pipeline front-end 504, a media engine 537, and graphics cores580A-580N. In some embodiments, ring interconnect 502 couples thegraphics processor to other processing units, including other graphicsprocessors or one or more general-purpose processor cores. In someembodiments, the graphics processor is one of many processors integratedwithin a multi-core processing system.

In some embodiments, graphics processor 500 receives batches of commandsvia ring interconnect 502. The incoming commands are interpreted by acommand streamer 503 in the pipeline front-end 504. In some embodiments,graphics processor 500 includes scalable execution logic to perform 3Dgeometry processing and media processing via the graphics core(s)580A-580N. For 3D geometry processing commands, command streamer 503supplies commands to geometry pipeline 536. For at least some mediaprocessing commands, command streamer 503 supplies the commands to avideo front end 534, which couples with a media engine 537. In someembodiments, media engine 537 includes a Video Quality Engine (VQE) 530for video and image post-processing and a multi-format encode/decode(MFX) 533 engine to provide hardware-accelerated media data encode anddecode. In some embodiments, geometry pipeline 536 and media engine 537each generate execution threads for the thread execution resourcesprovided by at least one graphics core 580A.

In some embodiments, graphics processor 500 includes scalable threadexecution resources featuring modular cores 580A-580N (sometimesreferred to as core slices), each having multiple sub-cores 550A-550N,560A-560N (sometimes referred to as core sub-slices). In someembodiments, graphics processor 500 can have any number of graphicscores 580A through 580N. In some embodiments, graphics processor 500includes a graphics core 580A having at least a first sub-core 550A anda second sub-core 560A. In other embodiments, the graphics processor isa low power processor with a single sub-core (e.g., 550A). In someembodiments, graphics processor 500 includes multiple graphics cores580A-580N, each including a set of first sub-cores 550A-550N and a setof second sub-cores 560A-560N. Each sub-core in the set of firstsub-cores 550A-550N includes at least a first set of execution units552A-552N and media/texture samplers 554A-554N. Each sub-core in the setof second sub-cores 560A-560N includes at least a second set ofexecution units 562A-562N and samplers 564A-564N. In some embodiments,each sub-core 550A-550N, 560A-560N shares a set of shared resources570A-570N. In some embodiments, the shared resources include sharedcache memory and pixel operation logic. Other shared resources may alsobe included in the various embodiments of the graphics processor.

Execution Units

FIG. 6 illustrates thread execution logic 600 including an array ofprocessing elements employed in some embodiments of a GPE. Elements ofFIG. 6 having the same reference numbers (or names) as the elements ofany other figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such.

In some embodiments, thread execution logic 600 includes a shaderprocessor 602, a thread dispatcher 604, instruction cache 606, ascalable execution unit array including a plurality of execution units608A-608N, a sampler 610, a data cache 612, and a data port 614. In oneembodiment the scalable execution unit array can dynamically scale byenabling or disabling one or more execution units (e.g., any ofexecution unit 608A, 608B, 608C, 608D, through 608N-1 and 608N) based onthe computational requirements of a workload. In one embodiment theincluded components are interconnected via an interconnect fabric thatlinks to each of the components. In some embodiments, thread executionlogic 600 includes one or more connections to memory, such as systemmemory or cache memory, through one or more of instruction cache 606,data port 614, sampler 610, and execution units 608A-608N. In someembodiments, each execution unit (e.g. 608A) is a stand-aloneprogrammable general purpose computational unit that is capable ofexecuting multiple simultaneous hardware threads while processingmultiple data elements in parallel for each thread. In variousembodiments, the array of execution units 608A-608N is scalable toinclude any number individual execution units.

In some embodiments, the execution units 608A-608N are primarily used toexecute shader programs. A shader processor 602 can process the variousshader programs and dispatch execution threads associated with theshader programs via a thread dispatcher 604. In one embodiment thethread dispatcher includes logic to arbitrate thread initiation requestsfrom the graphics and media pipelines and instantiate the requestedthreads on one or more execution unit in the execution units 608A-608N.For example, the geometry pipeline (e.g., 536 of FIG. 5) can dispatchvertex, tessellation, or geometry shaders to the thread execution logic600 (FIG. 6) for processing. In some embodiments, thread dispatcher 604can also process runtime thread spawning requests from the executingshader programs.

In some embodiments, the execution units 608A-608N support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. The execution units support vertex and geometry processing(e.g., vertex programs, geometry programs, vertex shaders), pixelprocessing (e.g., pixel shaders, fragment shaders) and general-purposeprocessing (e.g., compute and media shaders). Each of the executionunits 608A-608N is capable of multi-issue single instruction multipledata (SIMD) execution and multi-threaded operation enables an efficientexecution environment in the face of higher latency memory accesses.Each hardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state.Execution is multi-issue per clock to pipelines capable of integer,single and double precision floating point operations, SIMD branchcapability, logical operations, transcendental operations, and othermiscellaneous operations. While waiting for data from memory or one ofthe shared functions, dependency logic within the execution units608A-608N causes a waiting thread to sleep until the requested data hasbeen returned. While the waiting thread is sleeping, hardware resourcesmay be devoted to processing other threads. For example, during a delayassociated with a vertex shader operation, an execution unit can performoperations for a pixel shader, fragment shader, or another type ofshader program, including a different vertex shader.

Each execution unit in execution units 608A-608N operates on arrays ofdata elements. The number of data elements is the “execution size,” orthe number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 608A-608N support integer andfloating-point data types.

The execution unit instruction set includes SIMD instructions. Thevarious data elements can be stored as a packed data type in a registerand the execution unit will process the various elements based on thedata size of the elements. For example, when operating on a 256-bit widevector, the 256 bits of the vector are stored in a register and theexecution unit operates on the vector as four separate 64-bit packeddata elements (Quad-Word (QW) size data elements), eight separate 32-bitpacked data elements (Double Word (DW) size data elements), sixteenseparate 16-bit packed data elements (Word (W) size data elements), orthirty-two separate 8-bit data elements (byte (B) size data elements).However, different vector widths and register sizes are possible.

One or more internal instruction caches (e.g., 606) are included in thethread execution logic 600 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,612) are included to cache thread data during thread execution. In someembodiments, a sampler 610 is included to provide texture sampling for3D operations and media sampling for media operations. In someembodiments, sampler 610 includes specialized texture or media samplingfunctionality to process texture or media data during the samplingprocess before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 600 via thread spawningand dispatch logic. Once a group of geometric objects has been processedand rasterized into pixel data, pixel processor logic (e.g., pixelshader logic, fragment shader logic, etc.) within the shader processor602 is invoked to further compute output information and cause resultsto be written to output surfaces (e.g., color buffers, depth buffers,stencil buffers, etc.). In some embodiments, a pixel shader or fragmentshader calculates the values of the various vertex attributes that areto be interpolated across the rasterized object. In some embodiments,pixel processor logic within the shader processor 602 then executes anapplication programming interface (API)-supplied pixel or fragmentshader program. To execute the shader program, the shader processor 602dispatches threads to an execution unit (e.g., 608A) via threaddispatcher 604. In some embodiments, pixel shader 602 uses texturesampling logic in the sampler 610 to access texture data in texture mapsstored in memory. Arithmetic operations on the texture data and theinput geometry data compute pixel color data for each geometricfragment, or discards one or more pixels from further processing.

In some embodiments, the data port 614 provides a memory accessmechanism for the thread execution logic 600 output processed data tomemory for processing on a graphics processor output pipeline. In someembodiments, the data port 614 includes or couples to one or more cachememories (e.g., data cache 612) to cache data for memory access via thedata port.

FIG. 7 is a block diagram illustrating a graphics processor instructionformats 700 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments,instruction format 700 described and illustrated are macro-instructions,in that they are instructions supplied to the execution unit, as opposedto micro-operations resulting from instruction decode once theinstruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit instruction format 710. A 64-bitcompacted instruction format 730 is available for some instructionsbased on the selected instruction, instruction options, and number ofoperands. The native 128-bit instruction format 710 provides access toall instruction options, while some options and operations arerestricted in the 64-bit instruction format 730. The native instructionsavailable in the 64-bit instruction format 730 vary by embodiment. Insome embodiments, the instruction is compacted in part using a set ofindex values in an index field 713. The execution unit hardwarereferences a set of compaction tables based on the index values and usesthe compaction table outputs to reconstruct a native instruction in the128-bit instruction format 710.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 714 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). Forinstructions in the 128-bit instruction format 710 an exec-size field716 limits the number of data channels that will be executed inparallel. In some embodiments, exec-size field 716 is not available foruse in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 720, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode 712 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726 specifying, for example, whether directregister addressing mode or indirect register addressing mode is used.When direct register addressing mode is used, the register address ofone or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726, which specifies an address mode and/or anaccess mode for the instruction. In one embodiment the access mode isused to define a data access alignment for the instruction. Someembodiments support access modes including a 16-byte aligned access modeand a 1-byte aligned access mode, where the byte alignment of the accessmode determines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction may use 16-byte-aligned addressing for all sourceand destination operands.

In one embodiment, the address mode portion of the access/address modefield 726 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction directly provide the register address of one or moreoperands. When indirect register addressing mode is used, the registeraddress of one or more operands may be computed based on an addressregister value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 742 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 742 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 744 (e.g., call, jump (jmp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes amix of instructions, including synchronization instructions (e.g., wait,send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instructiongroup 748 includes component-wise arithmetic instructions (e.g., add,multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel mathgroup 748 performs the arithmetic operations in parallel across datachannels. The vector math group 750 includes arithmetic instructions(e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math groupperforms arithmetic such as dot product calculations on vector operands.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor800. Elements of FIG. 8 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 800 includes a graphics pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of graphics pipeline 820 or media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A-852B via a thread dispatcher831.

In some embodiments, execution units 852A-852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A-852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, graphics pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to graphics pipeline 820. Insome embodiments, if tessellation is not used, tessellation components(e.g., hull shader 811, tessellator 813, and domain shader 817) can bebypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A-852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper829 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer and depth test component 873 in the render output pipeline870 dispatches pixel shaders to convert the geometric objects into theirper pixel representations. In some embodiments, pixel shader logic isincluded in thread execution logic 850. In some embodiments, anapplication can bypass the rasterizer and depth test component 873 andaccess un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A-852B and associated cache(s) 851,texture and media sampler 854, and texture/sampler cache 858interconnect via a data port 856 to perform memory access andcommunicate with render output pipeline components of the processor. Insome embodiments, sampler 854, caches 851, 858 and execution units852A-852B each have separate memory access paths.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache 878and depth cache 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 837 and a video front end 834. In some embodiments, videofront end 834 receives pipeline commands from the command streamer 803.In some embodiments, media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 837 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, graphics pipeline 820 and media pipeline 830 areconfigurable to perform operations based on multiple graphics and mediaprogramming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL), Open Computing Language (OpenCL),and/or Vulkan graphics and compute API, all from the Khronos Group. Insome embodiments, support may also be provided for the Direct3D libraryfrom the Microsoft Corporation. In some embodiments, a combination ofthese libraries may be supported. Support may also be provided for theOpen Source Computer Vision Library (OpenCV). A future API with acompatible 3D pipeline would also be supported if a mapping can be madefrom the pipeline of the future API to the pipeline of the graphicsprocessor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 9B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. The solid lined boxes in FIG. 9A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 900 of FIG. 9A includes data fields to identify a targetclient 902 of the command, a command operation code (opcode) 904, andthe relevant data 906 for the command. A sub-opcode 905 and a commandsize 908 are also included in some commands.

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands.Once the command is received by the client unit, the client unit readsthe opcode 904 and, if present, sub-opcode 905 to determine theoperation to perform. The client unit performs the command usinginformation in data field 906. For some commands an explicit commandsize 908 is expected to specify the size of the command. In someembodiments, the command parser automatically determines the size of atleast some of the commands based on the command opcode. In someembodiments commands are aligned via multiples of a double word.

The flow diagram in FIG. 9B shows an exemplary graphics processorcommand sequence 910. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 maybegin with a pipeline flush command 912 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands. In responseto a pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command 912 is required immediatelybefore a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, commands for the return buffer state 916 are usedto configure a set of return buffers for the respective pipelines towrite data. Some pipeline operations require the allocation, selection,or configuration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments,configuring the return buffer state 916 includes selecting the size andnumber of return buffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930 or the media pipeline 924 beginning at themedia pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D statesetting commands for vertex buffer state, vertex element state, constantcolor state, depth buffer state, and other state variables that are tobe configured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based on the particular3D API in use. In some embodiments, 3D pipeline state 930 commands arealso able to selectively disable or bypass certain pipeline elements ifthose elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment, commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 910 followsthe media pipeline 924 path when performing media operations. Ingeneral, the specific use and manner of programming for the mediapipeline 924 depends on the media or compute operations to be performed.Specific media decode operations may be offloaded to the media pipelineduring media decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of commands to configure the mediapipeline state 940 are dispatched or placed into a command queue beforethe media object commands 942. In some embodiments, commands for themedia pipeline state 940 include data to configure the media pipelineelements that will be used to process the media objects. This includesdata to configure the video decode and video encode logic within themedia pipeline, such as encode or decode format. In some embodiments,commands for the media pipeline state 940 also support the use of one ormore pointers to “indirect” state elements that contain a batch of statesettings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia object commands 942 are queued, the media pipeline 924 istriggered via an execute command 944 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system 1000 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application1010, an operating system 1020, and at least one processor 1030. In someembodiments, processor 1030 includes a graphics processor 1032 and oneor more general-purpose processor core(s) 1034. The graphics application1010 and operating system 1020 each execute in the system memory 1050 ofthe data processing system.

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL) or the OpenGL Shader Language (GLSL). Theapplication also includes executable instructions 1014 in a machinelanguage suitable for execution by the general-purpose processor core1034. The application also includes graphics objects 1016 defined byvertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. The operating system 1020 can support agraphics API 1022 such as the Direct3D API, the OpenGL API, or theVulkan API. When the Direct3D API is in use, the operating system 1020uses a front-end shader compiler 1024 to compile any shader instructions1012 in HLSL into a lower-level shader language. The compilation may bea just-in-time (JIT) compilation or the application can perform shaderpre-compilation. In some embodiments, high-level shaders are compiledinto low-level shaders during the compilation of the 3D graphicsapplication 1010. In some embodiments, the shader instructions 1012 areprovided in an intermediate form, such as a version of the StandardPortable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 11 is a block diagram illustrating an IP core development system1100 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system1100 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility1130 can generate a software simulation 1110 of an IP core design in ahigh level programming language (e.g., C/C++). The software simulation1110 can be used to design, test, and verify the behavior of the IP coreusing a simulation model 1112. The simulation model 1112 may includefunctional, behavioral, and/or timing simulations. A register transferlevel (RTL) design 1115 can then be created or synthesized from thesimulation model 1112. The RTL design 1115 is an abstraction of thebehavior of the integrated circuit that models the flow of digitalsignals between hardware registers, including the associated logicperformed using the modeled digital signals. In addition to an RTLdesign 1115, lower-level designs at the logic level or transistor levelmay also be created, designed, or synthesized. Thus, the particulardetails of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by thedesign facility into a hardware model 1120, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3rdparty fabrication facility 1165 using non-volatile memory 1140 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 1150 or wireless connection 1160. Thefabrication facility 1165 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

Exemplary System on a Chip Integrated Circuit

FIGS. 12-14 illustrate exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included, includingadditional graphics processors/cores, peripheral interface controllers,or general purpose processor cores.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1200 that may be fabricated using one or more IPcores, according to an embodiment. Exemplary integrated circuit 1200includes one or more application processor(s) 1205 (e.g., processors),at least one graphics processor 1210, and may additionally include animage processor 1215 and/or a video processor 1220, any of which may bea modular IP core from the same or multiple different design facilities.Integrated circuit 1200 includes peripheral or bus logic including a USBcontroller 1225, UART controller 1230, an SPI/SDIO controller 1235, andan I2S/I2C controller 1240. Additionally, the integrated circuit caninclude a display device 1245 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 1250 and a mobileindustry processor interface (MIPI) display interface 1255. Storage maybe provided by a flash memory subsystem 1260 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 1265 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine1270.

FIG. 13 is a block diagram illustrating an exemplary graphics processor1310 of a system on a chip integrated circuit that may be fabricatedusing one or more IP cores, according to an embodiment. Graphicsprocessor 1310 can be a variant of the graphics processor 1210 of FIG.12. Graphics processor 1310 includes a vertex processor 1305 and one ormore fragment processor(s) 1315A1315N (e.g., 1315A, 1315B, 1315C, 1315D,through 1315N-1, and 1315N). Graphics processor 1310 can executedifferent shader programs via separate logic, such that the vertexprocessor 1305 is optimized to execute operations for vertex shaderprograms, while the one or more fragment processor(s) 1315A-1315Nexecute fragment (e.g., pixel) shading operations for fragment or pixelshader programs. The vertex processor 1305 performs the vertexprocessing stage of the 3D graphics pipeline and generates primitivesand vertex data. The fragment processor(s) 1315A-1315N use the primitiveand vertex data generated by the vertex processor 1305 to produce aframebuffer that is displayed on a display device. In one embodiment,the fragment processor(s) 1315A-1315N are optimized to execute fragmentshader programs as provided for in the OpenGL API, which may be used toperform similar operations as a pixel shader program as provided for inthe Direct 3D API.

Graphics processor 1310 additionally includes one or more memorymanagement units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuitinterconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B providefor virtual to physical address mapping for graphics processor 1310,including for the vertex processor 1305 and/or fragment processor(s)1315A-1315N, which may reference vertex or image/texture data stored inmemory, in addition to vertex or image/texture data stored in the one ormore cache(s) 1325A-1325B. In one embodiment the one or more MMU(s)1320A-1320B may be synchronized with other MMUs within the system,including one or more MMUs associated with the one or more applicationprocessor(s) 1205, image processor 1215, and/or video processor 1220 ofFIG. 12, such that each processor 1205-1220 can participate in a sharedor unified virtual memory system. The one or more circuitinterconnect(s) 1330A-1330B enable graphics processor 1310 to interfacewith other IP cores within the SoC, either via an internal bus of theSoC or via a direct connection, according to embodiments.

FIG. 14 is a block diagram illustrating an additional exemplary graphicsprocessor 1410 of a system on a chip integrated circuit that may befabricated using one or more IP cores, according to an embodiment.Graphics processor 1410 can be a variant of the graphics processor 1210of FIG. 12. Graphics processor 1410 includes the one or more MMU(s)1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s)1330A-1330B of the integrated circuit 1300 of FIG. 13.

Graphics processor 1410 includes one or more shader core(s) 1415A-1415N(e.g., 1415A, 1415B, 1415C, 1415D, 1415E, 1415F, through 1315N-1, and1315N), which provides for a unified shader core architecture in which asingle core or type or core can execute all types of programmable shadercode, including shader program code to implement vertex shaders,fragment shaders, and/or compute shaders. The exact number of shadercores present can vary among embodiments and implementations.Additionally, graphics processor 1410 includes an inter-core taskmanager 1405, which acts as a thread dispatcher to dispatch executionthreads to one or more shader core(s) 1415A-1415N and a tiling unit 1418to accelerate tiling operations for tile-based rendering, in whichrendering operations for a scene are subdivided in image space, forexample to exploit local spatial coherence within a scene or to optimizeuse of internal caches.

Exemplary Graphics Microarchitectures

In some embodiments, a graphics processing unit (GPU) is communicativelycoupled to host/processor cores to accelerate graphics operations,machine-learning operations, pattern analysis operations, and variousgeneral purpose GPU (GPGPU) functions. The GPU may be communicativelycoupled to the host processor/cores over a bus or another interconnect(e.g., a high-speed interconnect such as PCIe or NVLink). In otherembodiments, the GPU may be integrated on the same package or chip asthe cores and communicatively coupled to the cores over an internalprocessor bus/interconnect (i.e., internal to the package or chip).Regardless of the manner in which the GPU is connected, the processorcores may allocate work to the GPU in the form of sequences ofcommands/instructions contained in a work descriptor. The GPU then usesdedicated circuitry/logic for efficiently processing thesecommands/instructions.

In the following description, numerous specific details are set forth toprovide a more thorough understanding. However, it will be apparent toone of skill in the art that the embodiments described herein may bepracticed without one or more of these specific details. In otherinstances, well-known features have not been described to avoidobscuring the details of the present embodiments.

System Overview

FIG. 15 is a block diagram illustrating a computing system 1500configured to implement one or more aspects of the embodiments describedherein. The computing system 1500 includes a processing subsystem 1501having one or more processor(s) 1502 and a system memory 1504communicating via an interconnection path that may include a memory hub1505. The memory hub 1505 may be a separate component within a chipsetcomponent or may be integrated within the one or more processor(s) 1502.The memory hub 1505 couples with an I/O subsystem 1511 via acommunication link 1506. The I/O subsystem 1511 includes an I/O hub 1507that can enable the computing system 1500 to receive input from one ormore input device(s) 1508. Additionally, the I/O hub 1507 can enable adisplay controller, which may be included in the one or moreprocessor(s) 1502, to provide outputs to one or more display device(s)1510A. In one embodiment the one or more display device(s) 1510A coupledwith the I/O hub 1507 can include a local, internal, or embedded displaydevice.

In one embodiment the processing subsystem 1501 includes one or moreparallel processor(s) 1512 coupled to memory hub 1505 via a bus or othercommunication link 1513. The communication link 1513 may be one of anynumber of standards based communication link technologies or protocols,such as, but not limited to PCI Express, or may be a vendor specificcommunications interface or communications fabric. In one embodiment theone or more parallel processor(s) 1512 form a computationally focusedparallel or vector processing system that an include a large number ofprocessing cores and/or processing clusters, such as a many integratedcore (MIC) processor. In one embodiment the one or more parallelprocessor(s) 1512 form a graphics processing subsystem that can outputpixels to one of the one or more display device(s) 1510A coupled via theI/O Hub 1507. The one or more parallel processor(s) 1512 can alsoinclude a display controller and display interface (not shown) to enablea direct connection to one or more display device(s) 1510B.

Within the I/O subsystem 15115, a system storage unit 1514 can connectto the I/O hub 1507 to provide a storage mechanism for the computingsystem 1500. An I/O switch 1516 can be used to provide an interfacemechanism to enable connections between the I/O hub 1507 and othercomponents, such as a network adapter 1518 and/or wireless networkadapter 1519 that may be integrated into the platform, and various otherdevices that can be added via one or more add-in device(s) 1520. Thenetwork adapter 1518 can be an Ethernet adapter or another wired networkadapter. The wireless network adapter 1519 can include one or more of aWi-Fi, Bluetooth, near field communication (NFC), or other networkdevice that includes one or more wireless radios.

The computing system 1500 can include other components not explicitlyshown, including USB or other port connections, optical storage drives,video capture devices, and the like, may also be connected to the I/Ohub 1507. Communication paths interconnecting the various components inFIG. 15 may be implemented using any suitable protocols, such as PCI(Peripheral Component Interconnect) based protocols (e.g., PCI-Express),or any other bus or point-to-point communication interfaces and/orprotocol(s), such as the NV-Link high-speed interconnect, orinterconnect protocols known in the art.

In one embodiment, the one or more parallel processor(s) 1512incorporate circuitry optimized for graphics and video processing,including, for example, video output circuitry, and constitutes agraphics processing unit (GPU). In another embodiment, the one or moreparallel processor(s) 1512 incorporate circuitry optimized for generalpurpose processing, while preserving the underlying computationalarchitecture, described in greater detail herein. In yet anotherembodiment, components of the computing system 1500 may be integratedwith one or more other system elements on a single integrated circuit.For example, the one or more parallel processor(s), 1512 memory hub1505, processor(s) 1502, and I/O hub 1507 can be integrated into asystem on chip (SoC) integrated circuit. Alternatively, the componentsof the computing system 1500 can be integrated into a single package toform a system in package (SIP) configuration. In one embodiment at leasta portion of the components of the computing system 1500 can beintegrated into a multi-chip module (MCM), which can be interconnectedwith other multi-chip modules into a modular computing system.

It will be appreciated that the computing system 1500 shown herein isillustrative and that variations and modifications are possible. Theconnection topology, including the number and arrangement of bridges,the number of processor(s) 1502, and the number of parallel processor(s)1512, may be modified as desired. For instance, in some embodiments,system memory 1504 is connected to the processor(s) 1502 directly ratherthan through a bridge, while other devices communicate with systemmemory 1504 via the memory hub 1505 and the processor(s) 1502. In otheralternative topologies, the parallel processor(s) 1512 are connected tothe I/O hub 1507 or directly to one of the one or more processor(s)1502, rather than to the memory hub 1505. In other embodiments, the I/Ohub 1507 and memory hub 1505 may be integrated into a single chip. Someembodiments may include two or more sets of processor(s) 1502 attachedvia multiple sockets, which can couple with two or more instances of theparallel processor(s) 1512.

Some of the particular components shown herein are optional and may notbe included in all implementations of the computing system 1500. Forexample, any number of add-in cards or peripherals may be supported, orsome components may be eliminated. Furthermore, some architectures mayuse different terminology for components similar to those illustrated inFIG. 15. For example, the memory hub 1505 may be referred to as aNorthbridge in some architectures, while the I/O hub 1507 may bereferred to as a Southbridge.

FIG. 16A illustrates a parallel processor 1600, according to anembodiment. The various components of the parallel processor 1600 may beimplemented using one or more integrated circuit devices, such asprogrammable processors, application specific integrated circuits(ASICs), or field programmable gate arrays (FPGA). The illustratedparallel processor 1600 is a variant of the one or more parallelprocessor(s) 1512 shown in FIG. 15, according to an embodiment.

In one embodiment the parallel processor 1600 includes a parallelprocessing unit 1602. The parallel processing unit includes an I/O unit1604 that enables communication with other devices, including otherinstances of the parallel processing unit 1602. The I/O unit 1604 may bedirectly connected to other devices. In one embodiment the I/O unit 1604connects with other devices via the use of a hub or switch interface,such as memory hub 1505. The connections between the memory hub 1505 andthe I/O unit 1604 form a communication link 1513. Within the parallelprocessing unit 1602, the I/O unit 1604 connects with a host interface1606 and a memory crossbar 1616, where the host interface 1606 receivescommands directed to performing processing operations and the memorycrossbar 1616 receives commands directed to performing memoryoperations.

When the host interface 1606 receives a command buffer via the I/O unit1604, the host interface 1606 can direct work operations to performthose commands to a front end 1608. In one embodiment the front end 1608couples with a scheduler 1610, which is configured to distributecommands or other work items to a processing cluster array 1612. In oneembodiment the scheduler 1610 ensures that the processing cluster array1612 is properly configured and in a valid state before tasks aredistributed to the processing clusters of the processing cluster array1612. In one embodiment the scheduler 1610 is implemented via firmwarelogic executing on a microcontroller. The microcontroller implementedscheduler 1610 is configurable to perform complex scheduling and workdistribution operations at coarse and fine granularity, enabling rapidpreemption and context switching of threads executing on the processingarray 1612. In one embodiment, the host software can prove workloads forscheduling on the processing array 1612 via one of multiple graphicsprocessing doorbells. The workloads can then be automaticallydistributed across the processing array 1612 by the scheduler 1610 logicwithin the scheduler microcontroller.

The processing cluster array 1612 can include up to “N” processingclusters (e.g., cluster 1614A, cluster 1614B, through cluster 1614N).Each cluster 1614A-1614N of the processing cluster array 1612 canexecute a large number of concurrent threads. The scheduler 1610 canallocate work to the clusters 1614A-1614N of the processing clusterarray 1612 using various scheduling and/or work distribution algorithms,which may vary depending on the workload arising for each type ofprogram or computation. The scheduling can be handled dynamically by thescheduler 1610, or can be assisted in part by compiler logic duringcompilation of program logic configured for execution by the processingcluster array 1612. In one embodiment, different clusters 1614A-1614N ofthe processing cluster array 1612 can be allocated for processingdifferent types of programs or for performing different types ofcomputations.

The processing cluster array 1612 can be configured to perform varioustypes of parallel processing operations. In one embodiment theprocessing cluster array 1612 is configured to perform general-purposeparallel compute operations. For example, the processing cluster array1612 can include logic to execute processing tasks including filteringof video and/or audio data, performing modeling operations, includingphysics operations, and performing data transformations.

In one embodiment the processing cluster array 1612 is configured toperform parallel graphics processing operations. In embodiments in whichthe parallel processor 1600 is configured to perform graphics processingoperations, the processing cluster array 1612 can include additionallogic to support the execution of such graphics processing operations,including, but not limited to texture sampling logic to perform textureoperations, as well as tessellation logic and other vertex processinglogic. Additionally, the processing cluster array 1612 can be configuredto execute graphics processing related shader programs such as, but notlimited to vertex shaders, tessellation shaders, geometry shaders, andpixel shaders. The parallel processing unit 1602 can transfer data fromsystem memory via the I/O unit 1604 for processing. During processingthe transferred data can be stored to on-chip memory (e.g., parallelprocessor memory 1622) during processing, then written back to systemmemory.

In one embodiment, when the parallel processing unit 1602 is used toperform graphics processing, the scheduler 1610 can be configured todivide the processing workload into approximately equal sized tasks, tobetter enable distribution of the graphics processing operations tomultiple clusters 1614A-1614N of the processing cluster array 1612. Insome embodiments, portions of the processing cluster array 1612 can beconfigured to perform different types of processing. For example a firstportion may be configured to perform vertex shading and topologygeneration, a second portion may be configured to perform tessellationand geometry shading, and a third portion may be configured to performpixel shading or other screen space operations, to produce a renderedimage for display. Intermediate data produced by one or more of theclusters 1614A-1614N may be stored in buffers to allow the intermediatedata to be transmitted between clusters 1614A-1614N for furtherprocessing.

During operation, the processing cluster array 1612 can receiveprocessing tasks to be executed via the scheduler 1610, which receivescommands defining processing tasks from front end 1608. For graphicsprocessing operations, processing tasks can include indices of data tobe processed, e.g., surface (patch) data, primitive data, vertex data,and/or pixel data, as well as state parameters and commands defining howthe data is to be processed (e.g., what program is to be executed). Thescheduler 1610 may be configured to fetch the indices corresponding tothe tasks or may receive the indices from the front end 1608. The frontend 1608 can be configured to ensure the processing cluster array 1612is configured to a valid state before the workload specified by incomingcommand buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

Each of the one or more instances of the parallel processing unit 1602can couple with parallel processor memory 1622. The parallel processormemory 1622 can be accessed via the memory crossbar 1616, which canreceive memory requests from the processing cluster array 1612 as wellas the I/O unit 1604. The memory crossbar 1616 can access the parallelprocessor memory 1622 via a memory interface 1618. The memory interface1618 can include multiple partition units (e.g., partition unit 1620A,partition unit 1620B, through partition unit 1620N) that can each coupleto a portion (e.g., memory unit) of parallel processor memory 1622. Inone implementation the number of partition units 1620A-1620N isconfigured to be equal to the number of memory units, such that a firstpartition unit 1620A has a corresponding first memory unit 1624A, asecond partition unit 1620B has a corresponding memory unit 1624B, andan Nth partition unit 1620N has a corresponding Nth memory unit 1624N.In other embodiments, the number of partition units 1620A-1620N may notbe equal to the number of memory devices.

In various embodiments, the memory units 1624A-1624N can include varioustypes of memory devices, including dynamic random access memory (DRAM)or graphics random access memory, such as synchronous graphics randomaccess memory (SGRAM), including graphics double data rate (GDDR)memory. In one embodiment, the memory units 1624A-1624N may also include3D stacked memory, including but not limited to high bandwidth memory(HBM). Persons skilled in the art will appreciate that the specificimplementation of the memory units 1624A-1624N can vary, and can beselected from one of various conventional designs. Render targets, suchas frame buffers or texture maps may be stored across the memory units1624A-1624N, allowing partition units 1620A-1620N to write portions ofeach render target in parallel to efficiently use the availablebandwidth of parallel processor memory 1622. In some embodiments, alocal instance of the parallel processor memory 1622 may be excluded infavor of a unified memory design that utilizes system memory inconjunction with local cache memory.

In one embodiment, any one of the clusters 1614A-1614N of the processingcluster array 1612 can process data that will be written to any of thememory units 1624A-1624N within parallel processor memory 1622. Thememory crossbar 1616 can be configured to transfer the output of eachcluster 1614A-1614N to any partition unit 1620A-1620N or to anothercluster 1614A-1614N, which can perform additional processing operationson the output. Each cluster 1614A-1614N can communicate with the memoryinterface 1618 through the memory crossbar 1616 to read from or write tovarious external memory devices. In one embodiment the memory crossbar1616 has a connection to the memory interface 1618 to communicate withthe I/O unit 1604, as well as a connection to a local instance of theparallel processor memory 1622, enabling the processing units within thedifferent processing clusters 1614A-1614N to communicate with systemmemory or other memory that is not local to the parallel processing unit1602. In one embodiment the memory crossbar 1616 can use virtualchannels to separate traffic streams between the clusters 1614A-1614Nand the partition units 1620A-1620N.

While a single instance of the parallel processing unit 1602 isillustrated within the parallel processor 1600, any number of instancesof the parallel processing unit 1602 can be included. For example,multiple instances of the parallel processing unit 1602 can be providedon a single add-in card, or multiple add-in cards can be interconnected.The different instances of the parallel processing unit 1602 can beconfigured to inter-operate even if the different instances havedifferent numbers of processing cores, different amounts of localparallel processor memory, and/or other configuration differences. Forexample and in one embodiment, some instances of the parallel processingunit 1602 can include higher precision floating point units relative toother instances. Systems incorporating one or more instances of theparallel processing unit 1602 or the parallel processor 1600 can beimplemented in a variety of configurations and form factors, includingbut not limited to desktop, laptop, or handheld personal computers,servers, workstations, game consoles, and/or embedded systems.

FIG. 16B is a block diagram of a partition unit 1620, according to anembodiment. In one embodiment the partition unit 1620 is an instance ofone of the partition units 1620A-1620N of FIG. 16A. As illustrated, thepartition unit 1620 includes an L2 cache 1621, a frame buffer interface1625, and a ROP 1626 (raster operations unit). The L2 cache 1621 is aread/write cache that is configured to perform load and store operationsreceived from the memory crossbar 1616 and ROP 1626. Read misses andurgent write-back requests are output by L2 cache 1621 to frame bufferinterface 1625 for processing. Updates can also be sent to the framebuffer via the frame buffer interface 1625 for processing. In oneembodiment the frame buffer interface 1625 interfaces with one of thememory units in parallel processor memory, such as the memory units1624A-1624N of FIG. 16 (e.g., within parallel processor memory 1622).

In graphics applications, the ROP 1626 is a processing unit thatperforms raster operations such as stencil, z test, blending, and thelike. The ROP 1626 then outputs processed graphics data that is storedin graphics memory. In some embodiments the ROP 1626 includescompression logic to compress depth or color data that is written tomemory and decompress depth or color data that is read from memory. Thecompression logic can be lossless compression logic that makes use ofone or more of multiple compression algorithms. The type of compressionthat is performed by the ROP 1626 can vary based on the statisticalcharacteristics of the data to be compressed. For example, in oneembodiment, delta color compression is performed on depth and color dataon a per-tile basis.

In some embodiments, the ROP 1626 is included within each processingcluster (e.g., cluster 1614A-1614N of FIG. 16) instead of within thepartition unit 1620. In such embodiment, read and write requests forpixel data are transmitted over the memory crossbar 1616 instead ofpixel fragment data. The processed graphics data may be displayed on adisplay device, such as one of the one or more display device(s) 1510 ofFIG. 15, routed for further processing by the processor(s) 1502, orrouted for further processing by one of the processing entities withinthe parallel processor 1600 of FIG. 16A.

FIG. 16C is a block diagram of a processing cluster 1614 within aparallel processing unit, according to an embodiment. In one embodimentthe processing cluster is an instance of one of the processing clusters1614A-1614N of FIG. 16. The processing cluster 1614 can be configured toexecute many threads in parallel, where the term “thread” refers to aninstance of a particular program executing on a particular set of inputdata. In some embodiments, single-instruction, multiple-data (SIMD)instruction issue techniques are used to support parallel execution of alarge number of threads without providing multiple independentinstruction units. In other embodiments, single-instruction,multiple-thread (SIMT) techniques are used to support parallel executionof a large number of generally synchronized threads, using a commoninstruction unit configured to issue instructions to a set of processingengines within each one of the processing clusters. Unlike a SIMDexecution regime, where all processing engines typically executeidentical instructions, SIMT execution allows different threads to morereadily follow divergent execution paths through a given thread program.Persons skilled in the art will understand that a SIMD processing regimerepresents a functional subset of a SIMT processing regime.

Operation of the processing cluster 1614 can be controlled via apipeline manager 1632 that distributes processing tasks to SIMT parallelprocessors. The pipeline manager 1632 receives instructions from thescheduler 1610 of FIG. 16 and manages execution of those instructionsvia a graphics multiprocessor 1634 and/or a texture unit 1636. Theillustrated graphics multiprocessor 1634 is an exemplary instance of aSIMT parallel processor. However, various types of SIMT parallelprocessors of differing architectures may be included within theprocessing cluster 1614. One or more instances of the graphicsmultiprocessor 1634 can be included within a processing cluster 1614.The graphics multiprocessor 1634 can process data and a data crossbar1640 can be used to distribute the processed data to one of multiplepossible destinations, including other shader units. The pipelinemanager 1632 can facilitate the distribution of processed data byspecifying destinations for processed data to be distributed vis thedata crossbar 1640.

Each graphics multiprocessor 1634 within the processing cluster 1614 caninclude an identical set of functional execution logic (e.g., arithmeticlogic units, load-store units, etc.). The functional execution logic canbe configured in a pipelined manner in which new instructions can beissued before previous instructions are complete. The functionalexecution logic supports a variety of operations including integer andfloating point arithmetic, comparison operations, Boolean operations,bit-shifting, and computation of various algebraic functions. In oneembodiment the same functional-unit hardware can be leveraged to performdifferent operations and any combination of functional units may bepresent.

The instructions transmitted to the processing cluster 1614 constitutesa thread. A set of threads executing across the set of parallelprocessing engines is a thread group. A thread group executes the sameprogram on different input data. Each thread within a thread group canbe assigned to a different processing engine within a graphicsmultiprocessor 1634. A thread group may include fewer threads than thenumber of processing engines within the graphics multiprocessor 1634.When a thread group includes fewer threads than the number of processingengines, one or more of the processing engines may be idle during cyclesin which that thread group is being processed. A thread group may alsoinclude more threads than the number of processing engines within thegraphics multiprocessor 1634. When the thread group includes morethreads than the number of processing engines within the graphicsmultiprocessor 1634, processing can be performed over consecutive clockcycles. In one embodiment multiple thread groups can be executedconcurrently on a graphics multiprocessor 1634.

In one embodiment the graphics multiprocessor 1634 includes an internalcache memory to perform load and store operations. In one embodiment,the graphics multiprocessor 1634 can forego an internal cache and use acache memory (e.g., L1 cache 308) within the processing cluster 1614.Each graphics multiprocessor 1634 also has access to L2 caches withinthe partition units (e.g., partition units 1620A-1620N of FIG. 16) thatare shared among all processing clusters 1614 and may be used totransfer data between threads. The graphics multiprocessor 1634 may alsoaccess off-chip global memory, which can include one or more of localparallel processor memory and/or system memory. Any memory external tothe parallel processing unit 1602 may be used as global memory.Embodiments in which the processing cluster 1614 includes multipleinstances of the graphics multiprocessor 1634 can share commoninstructions and data, which may be stored in the L1 cache 1708.

Each processing cluster 1614 may include an MMU 1645 (memory managementunit) that is configured to map virtual addresses into physicaladdresses. In other embodiments, one or more instances of the MMU 1645may reside within the memory interface 1618 of FIG. 16. The MMU 1645includes a set of page table entries (PTEs) used to map a virtualaddress to a physical address of a tile (talk more about tiling) andoptionally a cache line index. The MMU 1645 may include addresstranslation lookaside buffers (TLB) or caches that may reside within thegraphics multiprocessor 1634 or the L1 cache or processing cluster 1614.The physical address is processed to distribute surface data accesslocality to allow efficient request interleaving among partition units.The cache line index may be used to determine whether a request for acache line is a hit or miss.

In graphics and computing applications, a processing cluster 1614 may beconfigured such that each graphics multiprocessor 1634 is coupled to atexture unit 1636 for performing texture mapping operations, e.g.,determining texture sample positions, reading texture data, andfiltering the texture data. Texture data is read from an internaltexture L1 cache (not shown) or in some embodiments from the L1 cachewithin graphics multiprocessor 1634 and is fetched from an L2 cache,local parallel processor memory, or system memory, as needed. Eachgraphics multiprocessor 1634 outputs processed tasks to the datacrossbar 1640 to provide the processed task to another processingcluster 1614 for further processing or to store the processed task in anL2 cache, local parallel processor memory, or system memory via thememory crossbar 1616. A preROP 1642 (pre-raster operations unit) isconfigured to receive data from graphics multiprocessor 1634, directdata to ROP units, which may be located with partition units asdescribed herein (e.g., partition units 1620A-1620N of FIG. 16). ThepreROP 1642 unit can perform optimizations for color blending, organizepixel color data, and perform address translations.

It will be appreciated that the core architecture described herein isillustrative and that variations and modifications are possible. Anynumber of processing units, e.g., graphics multiprocessor 1634, textureunits 1636, preROPs 1642, etc., may be included within a processingcluster 1614. Further, while only one processing cluster 1614 is shown,a parallel processing unit as described herein may include any number ofinstances of the processing cluster 1614. In one embodiment, eachprocessing cluster 1614 can be configured to operate independently ofother processing clusters 1614 using separate and distinct processingunits, L1 caches, etc.

FIG. 16D shows a graphics multiprocessor 1634, according to oneembodiment. In such embodiment the graphics multiprocessor 1634 coupleswith the pipeline manager 1632 of the processing cluster 1614. Thegraphics multiprocessor 1634 has an execution pipeline including but notlimited to an instruction cache 1652, an instruction unit 1654, anaddress mapping unit 1656, a register file 1658, one or more generalpurpose graphics processing unit (GPGPU) cores 1662, and one or moreload/store units 1666. The GPGPU cores 1662 and load/store units 1666are coupled with cache memory 1672 and shared memory 1670 via a memoryand cache interconnect 1668.

In one embodiment, the instruction cache 1652 receives a stream ofinstructions to execute from the pipeline manager 1632. The instructionsare cached in the instruction cache 1652 and dispatched for execution bythe instruction unit 1654. The instruction unit 1654 can dispatchinstructions as thread groups (e.g., warps), with each thread of thethread group assigned to a different execution unit within GPGPU core1662. An instruction can access any of a local, shared, or globaladdress space by specifying an address within a unified address space.The address mapping unit 1656 can be used to translate addresses in theunified address space into a distinct memory address that can beaccessed by the load/store units 1666.

The register file 1658 provides a set of registers for the functionalunits of the graphics multiprocessor 1724. The register file 1658provides temporary storage for operands connected to the data paths ofthe functional units (e.g., GPGPU cores 1662, load/store units 1666) ofthe graphics multiprocessor 1724. In one embodiment, the register file1658 is divided between each of the functional units such that eachfunctional unit is allocated a dedicated portion of the register file1658. In one embodiment, the register file 1658 is divided between thedifferent warps being executed by the graphics multiprocessor 1724.

The GPGPU cores 1662 can each include floating point units (FPUs) and/orinteger arithmetic logic units (ALUs) that are used to executeinstructions of the graphics multiprocessor 1724. The GPGPU cores 1662can be similar in architecture or can differ in architecture, accordingto embodiments. For example and in one embodiment, a first portion ofthe GPGPU cores 1662 include a single precision FPU and an integer ALUwhile a second portion of the GPGPU cores include a double precisionFPU. In one embodiment the FPUs can implement the IEEE 754-2008 standardfor floating point arithmetic or enable variable precision floatingpoint arithmetic. The graphics multiprocessor 1724 can additionallyinclude one or more fixed function or special function units to performspecific functions such as copy rectangle or pixel blending operations.In one embodiment one or more of the GPGPU cores can also include fixedor special function logic.

In one embodiment the GPGPU cores 1662 include SIMD logic capable ofperforming a single instruction on multiple sets of data. In oneembodiment GPGPU cores 1662 can physically execute SIMD4, SIMD8, andSIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32instructions. The SIMD instructions for the GPGPU cores can be generatedat compile time by a shader compiler or automatically generated whenexecuting programs written and compiled for single program multiple data(SPMD) or SIMT architectures. Multiple threads of a program configuredfor the SIMT execution model can executed via a single SIMD instruction.For example and in one embodiment, eight SIMT threads that perform thesame or similar operations can be executed in parallel via a singleSIMD8 logic unit.

The memory and cache interconnect 1668 is an interconnect network thatconnects each of the functional units of the graphics multiprocessor1724 to the register file 1658 and to the shared memory 1670. In oneembodiment, the memory and cache interconnect 1668 is a crossbarinterconnect that allows the load/store unit 1666 to implement load andstore operations between the shared memory 1670 and the register file1658. The register file 1658 can operate at the same frequency as theGPGPU cores 1662, thus data transfer between the GPGPU cores 1662 andthe register file 1658 is very low latency. The shared memory 1670 canbe used to enable communication between threads that execute on thefunctional units within the graphics multiprocessor 1634. The cachememory 1672 can be used as a data cache for example, to cache texturedata communicated between the functional units and the texture unit1636. The shared memory 1670 can also be used as a program managedcached. Threads executing on the GPGPU cores 1662 can programmaticallystore data within the shared memory in addition to the automaticallycached data that is stored within the cache memory 1672.

FIGS. 17A-17B illustrate additional graphics multiprocessors, accordingto embodiments. The illustrated graphics multiprocessors 1725, 1750 arevariants of the graphics multiprocessor 1634 of FIG. 16C. Theillustrated graphics multiprocessors 1725, 1750 can be configured as astreaming multiprocessor (SM) capable of simultaneous execution of alarge number of execution threads.

FIG. 17A shows a graphics multiprocessor 1725 according to an additionalembodiment. The graphics multiprocessor 1725 includes multipleadditional instances of execution resource units relative to thegraphics multiprocessor 1634 of FIG. 16D. For example, the graphicsmultiprocessor 1725 can include multiple instances of the instructionunit 1732A-1732B, register file 1734A-1734B, and texture unit(s)1744A-1744B. The graphics multiprocessor 1725 also includes multiplesets of graphics or compute execution units (e.g., GPGPU core1736A-1736B, GPGPU core 1737A-1737B, GPGPU core 1738A-1738B) andmultiple sets of load/store units 1740A-1740B. In one embodiment theexecution resource units have a common instruction cache 1730, textureand/or data cache memory 1742, and shared memory 1746.

The various components can communicate via an interconnect fabric 1727.In one embodiment the interconnect fabric 1727 includes one or morecrossbar switches to enable communication between the various componentsof the graphics multiprocessor 1725. In one embodiment the interconnectfabric 1727 is a separate, high-speed network fabric layer upon whicheach component of the graphics multiprocessor 1725 is stacked. Thecomponents of the graphics multiprocessor 1725 communicate with remotecomponents via the interconnect fabric 1727. For example, the GPGPUcores 1736A-1736B, 1737A-1737B, and 1737A-1738B can each communicatewith shared memory 1746 via the interconnect fabric 1727. Theinterconnect fabric 1727 can arbitrate communication within the graphicsmultiprocessor 1725 to ensure a fair bandwidth allocation betweencomponents.

FIG. 17B shows a graphics multiprocessor 1750 according to an additionalembodiment. The graphics processor includes multiple sets of executionresources 1756A-1756D, where each set of execution resource includesmultiple instruction units, register files, GPGPU cores, and load storeunits, as illustrated in FIG. 16D and FIG. 17A. The execution resources1756A-1756D can work in concert with texture unit(s) 1760A-1760D fortexture operations, while sharing an instruction cache 1754, and sharedmemory 1762. In one embodiment the execution resources 1756A-1756D canshare an instruction cache 1754 and shared memory 1762, as well asmultiple instances of a texture and/or data cache memory 1758A-1758B.The various components can communicate via an interconnect fabric 1752similar to the interconnect fabric 1727 of FIG. 17A.

Persons skilled in the art will understand that the architecturedescribed in FIGS. 15, 16A-16D, and 17A-17B are descriptive and notlimiting as to the scope of the present embodiments. Thus, thetechniques described herein may be implemented on any properlyconfigured processing unit, including, without limitation, one or moremobile application processors, one or more desktop or server centralprocessing units (CPUs) including multi-core CPUs, one or more parallelprocessing units, such as the parallel processing unit 1602 of FIG. 16,as well as one or more graphics processors or special purpose processingunits, without departure from the scope of the embodiments describedherein.

In some embodiments a parallel processor or GPGPU as described herein iscommunicatively coupled to host/processor cores to accelerate graphicsoperations, machine-learning operations, pattern analysis operations,and various general purpose GPU (GPGPU) functions. The GPU may becommunicatively coupled to the host processor/cores over a bus or otherinterconnect (e.g., a high speed interconnect such as PCIe or NVLink).In other embodiments, the GPU may be integrated on the same package orchip as the cores and communicatively coupled to the cores over aninternal processor bus/interconnect (i.e., internal to the package orchip). Regardless of the manner in which the GPU is connected, theprocessor cores may allocate work to the GPU in the form of sequences ofcommands/instructions contained in a work descriptor. The GPU then usesdedicated circuitry/logic for efficiently processing thesecommands/instructions.

Techniques for GPU to Host Processor Interconnection

FIG. 18A illustrates an exemplary architecture in which a plurality ofGPUs 1810-1813 are communicatively coupled to a plurality of multi-coreprocessors 1805-1806 over high-speed links 1840-1843 (e.g., buses,point-to-point interconnects, etc.). In one embodiment, the high-speedlinks 1840-1843 support a communication throughput of 4 GB/s, 30 GB/s,80 GB/s or higher, depending on the implementation. Various interconnectprotocols may be used including, but not limited to, PCIe 4.0 or 5.0 andNVLink 2.0. However, the underlying principles of the invention are notlimited to any particular communication protocol or throughput.

In addition, in one embodiment, two or more of the GPUs 1810-1813 areinterconnected over high-speed links 1844-1845, which may be implementedusing the same or different protocols/links than those used forhigh-speed links 1840-1843. Similarly, two or more of the multi-coreprocessors 1805-1806 may be connected over high speed link 1833 whichmay be symmetric multi-processor (SMP) buses operating at 20 GB/s, 30GB/s, 120 GB/s or higher. Alternatively, all communication between thevarious system components shown in FIG. 18A may be accomplished usingthe same protocols/links (e.g., over a common interconnection fabric).As mentioned, however, the underlying principles of the invention arenot limited to any particular type of interconnect technology.

In one embodiment, each multi-core processor 1805-1806 iscommunicatively coupled to a processor memory 1801-1802, via memoryinterconnects 1830-1831, respectively, and each GPU 1810-1813 iscommunicatively coupled to GPU memory 1820-1823 over GPU memoryinterconnects 1850-1853, respectively. The memory interconnects1830-1831 and 1850-1853 may utilize the same or different memory accesstechnologies. By way of example, and not limitation, the processormemories 1801-1802 and GPU memories 1820-1823 may be volatile memoriessuch as dynamic random access memories (DRAMs) (including stackedDRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or HighBandwidth Memory (HBM) and/or may be non-volatile memories such as 3DXPoint or Nano-Ram. In one embodiment, some portion of the memories maybe volatile memory and another portion may be non-volatile memory (e.g.,using a two-level memory (2LM) hierarchy).

As described below, although the various processors 1805-1806 and GPUs1810-1813 may be physically coupled to a particular memory 1801-1802,1820-1823, respectively, a unified memory architecture may beimplemented in which the same virtual system address space (alsoreferred to as the “effective address” space) is distributed among allof the various physical memories. For example, processor memories1801-1802 may each comprise 64 GB of the system memory address space andGPU memories 1820-1823 may each comprise 32 GB of the system memoryaddress space (resulting in a total of 256 GB addressable memory in thisexample).

FIG. 18B illustrates additional details for an interconnection between amulti-core processor 1807 and a graphics acceleration module 1846 inaccordance with one embodiment. The graphics acceleration module 1846may include one or more GPU chips integrated on a line card which iscoupled to the processor 1807 via the high-speed link 1840.Alternatively, the graphics acceleration module 1846 may be integratedon the same package or chip as the processor 1807.

The illustrated processor 1807 includes a plurality of cores1860A-1860D, each with a translation lookaside buffer 1861A-1861D andone or more caches 1862A-1862D. The cores may include various othercomponents for executing instructions and processing data which are notillustrated to avoid obscuring the underlying principles of theinvention (e.g., instruction fetch units, branch prediction units,decoders, execution units, reorder buffers, etc.). The caches1862A-1862D may comprise level 1 (L1) and level 2 (L2) caches. Inaddition, one or more shared caches 1826 may be included in the cachinghierarchy and shared by sets of the cores 1860A-1860D. For example, oneembodiment of the processor 1807 includes 24 cores, each with its own L1cache, twelve shared L2 caches, and twelve shared L3 caches. In thisembodiment, one of the L2 and L3 caches are shared by two adjacentcores. The processor 1807 and the graphics accelerator integrationmodule 1846 connect with system memory 1841, which may include processormemories 1801-1802

Coherency is maintained for data and instructions stored in the variouscaches 1862A-1862D, 1856 and system memory 1841 via inter-corecommunication over a coherence bus 1864. For example, each cache mayhave cache coherency logic/circuitry associated therewith to communicateto over the coherence bus 1864 in response to detected reads or writesto particular cache lines. In one implementation, a cache snoopingprotocol is implemented over the coherence bus 1864 to snoop cacheaccesses. Cache snooping/coherency techniques are well understood bythose of skill in the art and will not be described in detail here toavoid obscuring the underlying principles of the invention.

In one embodiment, a proxy circuit 1825 communicatively couples thegraphics acceleration module 1846 to the coherence bus 1864, allowingthe graphics acceleration module 1846 to participate in the cachecoherence protocol as a peer of the cores. In particular, an interface1835 provides connectivity to the proxy circuit 1825 over high-speedlink 1840 (e.g., a PCIe bus, NVLink, etc.) and an interface 1837connects the graphics acceleration module 1846 to the link 1840.

In one implementation, an accelerator integration circuit 1836 providescache management, memory access, context management, and interruptmanagement services on behalf of a plurality of graphics processingengines 1831, 1832, N of the graphics acceleration module 1846. Thegraphics processing engines 1831, 1832, N may each comprise a separategraphics processing unit (GPU). Alternatively, the graphics processingengines 1831, 1832, N may comprise different types of graphicsprocessing engines within a GPU such as graphics execution units, mediaprocessing engines (e.g., video encoders/decoders), samplers, and blitengines. In other words, the graphics acceleration module may be a GPUwith a plurality of graphics processing engines 1831-1832, N or thegraphics processing engines 1831-1832, N may be individual GPUsintegrated on a common package, line card, or chip.

In one embodiment, the accelerator integration circuit 1836 includes amemory management unit (MMU) 1839 for performing various memorymanagement functions such as virtual-to-physical memory translations(also referred to as effective-to-real memory translations) and memoryaccess protocols for accessing system memory 1841. The MMU 1839 may alsoinclude a translation lookaside buffer (TLB) (not shown) for caching thevirtual/effective to physical/real address translations. In oneimplementation, a cache 1838 stores commands and data for efficientaccess by the graphics processing engines 1831-1832, N. In oneembodiment, the data stored in cache 1838 and graphics memories1833-1834, N is kept coherent with the core caches 1862A-1862D, 1856 andsystem memory 1811. As mentioned, this may be accomplished via proxycircuit 1825 which takes part in the cache coherency mechanism on behalfof cache 1838 and memories 1833-1834, N (e.g., sending updates to thecache 1838 related to modifications/accesses of cache lines on processorcaches 1862A-1862D, 1856 and receiving updates from the cache 1838).

A set of registers 1845 store context data for threads executed by thegraphics processing engines 1831-1832, N and a context managementcircuit 1848 manages the thread contexts. For example, the contextmanagement circuit 1848 may perform save and restore operations to saveand restore contexts of the various threads during contexts switches(e.g., where a first thread is saved and a second thread is stored sothat the second thread can be execute by a graphics processing engine).For example, on a context switch, the context management circuit 1848may store current register values to a designated region in memory(e.g., identified by a context pointer). It may then restore theregister values when returning to the context. In one embodiment, aninterrupt management circuit 1847 receives and processes interruptsreceived from system devices.

In one implementation, virtual/effective addresses from a graphicsprocessing engine 1831 are translated to real/physical addresses insystem memory 1811 by the MMU 1839. One embodiment of the acceleratorintegration circuit 1836 supports multiple (e.g., 4, 8, 16) graphicsaccelerator modules 1846 and/or other accelerator devices. The graphicsaccelerator module 1846 may be dedicated to a single applicationexecuted on the processor 1807 or may be shared between multipleapplications. In one embodiment, a virtualized graphics executionenvironment is presented in which the resources of the graphicsprocessing engines 1831-1832, N are shared with multiple applications orvirtual machines (VMs). The resources may be subdivided into “slices”which are allocated to different VMs and/or applications based on theprocessing requirements and priorities associated with the VMs and/orapplications.

Thus, the accelerator integration circuit acts as a bridge to the systemfor the graphics acceleration module 1846 and provides addresstranslation and system memory cache services. In addition, theaccelerator integration circuit 1836 may provide virtualizationfacilities for the host processor to manage virtualization of thegraphics processing engines, interrupts, and memory management.

Because hardware resources of the graphics processing engines 1831-1832,N are mapped explicitly to the real address space seen by the hostprocessor 1807, any host processor can address these resources directlyusing an effective address value. One function of the acceleratorintegration circuit 1836, in one embodiment, is the physical separationof the graphics processing engines 1831-1832, N so that they appear tothe system as independent units.

As mentioned, in the illustrated embodiment, one or more graphicsmemories 1833-1834, M are coupled to each of the graphics processingengines 1831-1832, N, respectively. The graphics memories 1833-1834, Mstore instructions and data being processed by each of the graphicsprocessing engines 1831-1832, N. The graphics memories 1833-1834, M maybe volatile memories such as DRAMs (including stacked DRAMs), GDDRmemory (e.g., GDDR5, GDDR6), or HBM, and/or may be non-volatile memoriessuch as 3D XPoint or Nano-Ram.

In one embodiment, to reduce data traffic over link 1840, biasingtechniques are used to ensure that the data stored in graphics memories1833-1834, M is data which will be used most frequently by the graphicsprocessing engines 1831-1832, N and preferably not used by the cores1860A-1860D (at least not frequently). Similarly, the biasing mechanismattempts to keep data needed by the cores (and preferably not thegraphics processing engines 1831-1832, N) within the caches 1862A-1862D,1856 of the cores and system memory 1811.

FIG. 18C illustrates another embodiment in which the acceleratorintegration circuit 1836 is integrated within the processor 1807. Inthis embodiment, the graphics processing engines 1831-1832, Ncommunicate directly over the high-speed link 1840 to the acceleratorintegration circuit 1836 via interface 1837 and interface 1835 (which,again, may be utilize any form of bus or interface protocol). Theaccelerator integration circuit 1836 may perform the same operations asthose described with respect to FIG. 18B, but potentially at a higherthroughput given its close proximity to the coherency bus 1862 andcaches 1862A-1862D, 1826.

One embodiment supports different programming models including adedicated-process programming model (no graphics acceleration modulevirtualization) and shared programming models (with virtualization). Thelatter may include programming models which are controlled by theaccelerator integration circuit 1836 and programming models which arecontrolled by the graphics acceleration module 1846.

In one embodiment of the dedicated process model, graphics processingengines 1831-1832, N are dedicated to a single application or processunder a single operating system. The single application can funnel otherapplication requests to the graphics engines 1831-1832, N, providingvirtualization within a VM/partition.

In the dedicated-process programming models, the graphics processingengines 1831-1832, N, may be shared by multiple VM/applicationpartitions. The shared models require a system hypervisor to virtualizethe graphics processing engines 1831-1832, N to allow access by eachoperating system. For single-partition systems without a hypervisor, thegraphics processing engines 1831-1832, N are owned by the operatingsystem. In both cases, the operating system can virtualize the graphicsprocessing engines 1831-1832, N to provide access to each process orapplication.

For the shared programming model, the graphics acceleration module 1846or an individual graphics processing engine 1831-1832, N selects aprocess element using a process handle. In one embodiment, processelements are stored in system memory 1811 and are addressable using theeffective address to real address translation techniques describedherein. The process handle may be an implementation-specific valueprovided to the host process when registering its context with thegraphics processing engine 1831-1832, N (that is, calling systemsoftware to add the process element to the process element linked list).The lower 16-bits of the process handle may be the offset of the processelement within the process element linked list.

FIG. 18D illustrates an exemplary accelerator integration slice 1890. Asused herein, a “slice” comprises a specified portion of the processingresources of the accelerator integration circuit 1836. Applicationeffective address space 1882 within system memory 1811 stores processelements 1883. In one embodiment, the process elements 1883 are storedin response to GPU invocations 1881 from applications 1880 executed onthe processor 1807. A process element 1883 contains the process statefor the corresponding application 1880. A work descriptor (WD) 1884contained in the process element 1883 can be a single job requested byan application or may contain a pointer to a queue of jobs. In thelatter case, the WD 1884 is a pointer to the job request queue in theapplication's address space 1882.

The graphics acceleration module 1846 and/or the individual graphicsprocessing engines 1831-1832, N can be shared by all or a subset of theprocesses in the system. Embodiments of the invention include aninfrastructure for setting up the process state and sending a WD 1884 toa graphics acceleration module 1846 to start a job in a virtualizedenvironment.

In one implementation, the dedicated-process programming model isimplementation-specific. In this model, a single process owns thegraphics acceleration module 1846 or an individual graphics processingengine 1831. Because the graphics acceleration module 1846 is owned by asingle process, the hypervisor initializes the accelerator integrationcircuit 1836 for the owning partition and the operating systeminitializes the accelerator integration circuit 1836 for the owningprocess at the time when the graphics acceleration module 1846 isassigned.

In operation, a WD fetch unit 1891 in the accelerator integration slice1890 fetches the next WD 1884 which includes an indication of the workto be done by one of the graphics processing engines of the graphicsacceleration module 1846. Data from the WD 1884 may be stored inregisters 1845 and used by the MMU 1839, interrupt management circuit1847 and/or context management circuit 1846 as illustrated. For example,one embodiment of the MMU 1839 includes segment/page walk circuitry foraccessing segment/page tables 1886 within the OS virtual address space1885. The interrupt management circuit 1847 may process interrupt events1892 received from the graphics acceleration module 1846. Whenperforming graphics operations, an effective address 1893 generated by agraphics processing engine 1831-1832, N is translated to a real addressby the MMU 1839.

In one embodiment, the same set of registers 1845 are duplicated foreach graphics processing engine 1831-1832, N and/or graphicsacceleration module 1846 and may be initialized by the hypervisor oroperating system. Each of these duplicated registers may be included inan accelerator integration slice 1890. Exemplary registers that may beinitialized by the hypervisor are shown in Table 1.

TABLE 1 Hypervisor Initialized Registers 1 Slice Control Register 2 RealAddress (RA) Scheduled Processes Area Pointer 3 Authority Mask OverrideRegister 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector TableEntry Limit 6 State Register 7 Logical Partition ID 8 Real address (RA)Hypervisor Accelerator Utilization Record Pointer 9 Storage DescriptionRegister

Exemplary registers that may be initialized by the operating system areshown in Table 2.

TABLE 2 Operating System Initialized Registers 1 Process and ThreadIdentification 2 Effective Address (EA) Context Save/Restore Pointer 3Virtual Address (VA) Accelerator Utilization Record Pointer 4 VirtualAddress (VA) Storage Segment Table Pointer 5 Authority Mask 6 Workdescriptor

In one embodiment, each WD 1884 is specific to a particular graphicsacceleration module 1846 and/or graphics processing engine 1831-1832, N.It contains all the information a graphics processing engine 1831-1832,N requires to do its work or it can be a pointer to a memory locationwhere the application has set up a command queue of work to becompleted.

FIG. 18E illustrates additional details for one embodiment of a sharedmodel. This embodiment includes a hypervisor real address space 1898 inwhich a process element list 1899 is stored. The hypervisor real addressspace 1898 is accessible via a hypervisor 1896 which virtualizes thegraphics acceleration module engines for the operating system 1895.

The shared programming models allow for all or a subset of processesfrom all or a subset of partitions in the system to use a graphicsacceleration module 1846. There are two programming models where thegraphics acceleration module 1846 is shared by multiple processes andpartitions: time-sliced shared and graphics directed shared.

In this model, the system hypervisor 1896 owns the graphics accelerationmodule 1846 and makes its function available to all operating systems1895. For a graphics acceleration module 1846 to support virtualizationby the system hypervisor 1896, the graphics acceleration module 1846 mayadhere to the following requirements: 1) An application's job requestmust be autonomous (that is, the state does not need to be maintainedbetween jobs), or the graphics acceleration module 1846 must provide acontext save and restore mechanism. 2) An application's job request isguaranteed by the graphics acceleration module 1846 to complete in aspecified amount of time, including any translation faults, or thegraphics acceleration module 1846 provides the ability to preempt theprocessing of the job. 3) The graphics acceleration module 1846 must beguaranteed fairness between processes when operating in the directedshared programming model.

In one embodiment, for the shared model, the application 1880 isrequired to make an operating system 1895 system call with a graphicsacceleration module 1846 type, a work descriptor (WD), an authority maskregister (AMR) value, and a context save/restore area pointer (CSRP).The graphics acceleration module 1846 type describes the targetedacceleration function for the system call. The graphics accelerationmodule 1846 type may be a system-specific value. The WD is formattedspecifically for the graphics acceleration module 1846 and can be in theform of a graphics acceleration module 1846 command, an effectiveaddress pointer to a user-defined structure, an effective addresspointer to a queue of commands, or any other data structure to describethe work to be done by the graphics acceleration module 1846. In oneembodiment, the AMR value is the AMR state to use for the currentprocess. The value passed to the operating system is similar to anapplication setting the AMR. If the accelerator integration circuit 1836and graphics acceleration module 1846 implementations do not support aUser Authority Mask Override Register (UAMOR), the operating system mayapply the current UAMOR value to the AMR value before passing the AMR inthe hypervisor call. The hypervisor 1896 may optionally apply thecurrent Authority Mask Override Register (AMOR) value before placing theAMR into the process element 1883. In one embodiment, the CSRP is one ofthe registers 1845 containing the effective address of an area in theapplication's address space 1882 for the graphics acceleration module1846 to save and restore the context state. This pointer is optional ifno state is required to be saved between jobs or when a job ispreempted. The context save/restore area may be pinned system memory.

Upon receiving the system call, the operating system 1895 may verifythat the application 1880 has registered and been given the authority touse the graphics acceleration module 1846. The operating system 1895then calls the hypervisor 1896 with the information shown in Table 3.

TABLE 3 OS to Hypervisor Call Parameters 1 A work descriptor (WD) 2 AnAuthority Mask Register (AMR) value (potentially masked). 3 An effectiveaddress (EA) Context Save/Restore Area Pointer (CSRP) 4 A process ID(PID) and optional thread ID (TID) 5 A virtual address (VA) acceleratorutilization record pointer (AURP) 6 The virtual address of the storagesegment table pointer (SSTP) 7 A logical interrupt service number (LISN)

Upon receiving the hypervisor call, the hypervisor 1896 verifies thatthe operating system 1895 has registered and been given the authority touse the graphics acceleration module 1846. The hypervisor 1896 then putsthe process element 1883 into the process element linked list for thecorresponding graphics acceleration module 1846 type. The processelement may include the information shown in Table 4.

TABLE 4 Process Element Information  1 A work descriptor (WD)  2 AnAuthority Mask Register (AMR) value (potentially masked).  3 Aneffective address (EA) Context Save/Restore Area Pointer (CSRP)  4 Aprocess ID (PID) and optional thread ID (TID)  5 A virtual address (VA)accelerator utilization record pointer (AURP)  6 The virtual address ofthe storage segment table pointer (SSTP)  7 A logical interrupt servicenumber (LISN)  8 Interrupt vector table, derived from the hypervisorcall parameters.  9 A state register (SR) value 10 A logical partitionID (LPID) 11 A real address (RA) hypervisor accelerator utilizationrecord pointer 12 The Storage Descriptor Register (SDR)

In one embodiment, the hypervisor initializes a plurality of acceleratorintegration slice 1890 registers 1845.

As illustrated in FIG. 18F, one embodiment of the invention employs aunified memory addressable via a common virtual memory address spaceused to access the physical processor memories 1801-1802 and GPUmemories 1820-1823. In this implementation, operations executed on theGPUs 1810-1813 utilize the same virtual/effective memory address spaceto access the processors memories 1801-1802 and vice versa, therebysimplifying programmability. In one embodiment, a first portion of thevirtual/effective address space is allocated to the processor memory1801, a second portion to the second processor memory 1802, a thirdportion to the GPU memory 1820, and so on. The entire virtual/effectivememory space (sometimes referred to as the effective address space) isthereby distributed across each of the processor memories 1801-1802 andGPU memories 1820-1823, allowing any processor or GPU to access anyphysical memory with a virtual address mapped to that memory.

In one embodiment, bias/coherence management circuitry 1894A-1894Ewithin one or more of the MMUs 1839A-1839E ensures cache coherencebetween the caches of the host processors (e.g., 1805) and the GPUs1810-1813 and implements biasing techniques indicating the physicalmemories in which certain types of data should be stored. While multipleinstances of bias/coherence management circuitry 1894A-1894E areillustrated in FIG. 18F, the bias/coherence circuitry may be implementedwithin the MMU of one or more host processors 1805 and/or within theaccelerator integration circuit 1836.

One embodiment allows GPU-attached memory 1820-1823 to be mapped as partof system memory, and accessed using shared virtual memory (SVM)technology, but without suffering the typical performance drawbacksassociated with full system cache coherence. The ability to GPU-attachedmemory 1820-1823 to be accessed as system memory without onerous cachecoherence overhead provides a beneficial operating environment for GPUoffload. This arrangement allows the host processor 1805 software tosetup operands and access computation results, without the overhead oftradition I/O DMA data copies. Such traditional copies involve drivercalls, interrupts and memory mapped I/O (MMIO) accesses that are allinefficient relative to simple memory accesses. At the same time, theability to access GPU attached memory 1820-1823 without cache coherenceoverheads can be critical to the execution time of an offloadedcomputation. In cases with substantial streaming write memory traffic,for example, cache coherence overhead can significantly reduce theeffective write bandwidth seen by a GPU 1810-1813. The efficiency ofoperand setup, the efficiency of results access, and the efficiency ofGPU computation all play a role in determining the effectiveness of GPUoffload.

In one implementation, the selection of between GPU bias and hostprocessor bias is driven by a bias tracker data structure. A bias tablemay be used, for example, which may be a page-granular structure (i.e.,controlled at the granularity of a memory page) that includes 1 or 2bits per GPU-attached memory page. The bias table may be implemented ina stolen memory range of one or more GPU-attached memories 1820-1823,with or without a bias cache in the GPU 1810-1813 (e.g., to cachefrequently/recently used entries of the bias table). Alternatively, theentire bias table may be maintained within the GPU.

In one implementation, the bias table entry associated with each accessto the GPU-attached memory 1820-1823 is accessed prior the actual accessto the GPU memory, causing the following operations. First, localrequests from the GPU 1810-1813 that find their page in GPU bias areforwarded directly to a corresponding GPU memory 1820-1823. Localrequests from the GPU that find their page in host bias are forwarded tothe processor 1805 (e.g., over a high-speed link as discussed above). Inone embodiment, requests from the processor 1805 that find the requestedpage in host processor bias complete the request like a normal memoryread. Alternatively, requests directed to a GPU-biased page may beforwarded to the GPU 1810-1813. The GPU may then transition the page toa host processor bias if it is not currently using the page.

The bias state of a page can be changed either by a software-basedmechanism, a hardware-assisted software-based mechanism, or, for alimited set of cases, a purely hardware-based mechanism.

One mechanism for changing the bias state employs an API call (e.g.OpenCL), which, in turn, calls the GPU's device driver which, in turn,sends a message (or enqueues a command descriptor) to the GPU directingit to change the bias state and, for some transitions, perform a cacheflushing operation in the host. The cache flushing operation is requiredfor a transition from host processor 1805 bias to GPU bias, but is notrequired for the opposite transition.

In one embodiment, cache coherency is maintained by temporarilyrendering GPU-biased pages uncacheable by the host processor 1805. Toaccess these pages, the processor 1805 may request access from the GPU1810 which may or may not grant access right away, depending on theimplementation. Thus, to reduce communication between the processor 1805and GPU 1810 it is beneficial to ensure that GPU-biased pages are thosewhich are required by the GPU but not the host processor 1805 and viceversa.

Graphics Processing Pipeline

FIG. 19 illustrates a graphics processing pipeline 1900, according to anembodiment. In one embodiment a graphics processor can implement theillustrated graphics processing pipeline 1900. The graphics processorcan be included within the parallel processing subsystems as describedherein, such as the parallel processor 1600 of FIG. 16, which, in oneembodiment, is a variant of the parallel processor(s) 1512 of FIG. 15.The various parallel processing systems can implement the graphicsprocessing pipeline 1900 via one or more instances of the parallelprocessing unit (e.g., parallel processing unit 1602 of FIG. 16) asdescribed herein. For example, a shader unit (e.g., graphicsmultiprocessor 1634 of FIG. 17) may be configured to perform thefunctions of one or more of a vertex processing unit 1904, atessellation control processing unit 1908, a tessellation evaluationprocessing unit 1912, a geometry processing unit 1916, and afragment/pixel processing unit 1924. The functions of data assembler1902, primitive assemblers 1906, 1914, 1918, tessellation unit 1910,rasterizer 1922, and raster operations unit 1926 may also be performedby other processing engines within a processing cluster (e.g.,processing cluster 1614 of FIG. 17) and a corresponding partition unit(e.g., partition unit 220A-220N of FIG. 16). The graphics processingpipeline 1900 may also be implemented using dedicated processing unitsfor one or more functions. In one embodiment, one or more portions ofthe graphics processing pipeline 1900 can be performed by parallelprocessing logic within a general purpose processor (e.g., CPU). In oneembodiment, one or more portions of the graphics processing pipeline1900 can access on-chip memory (e.g., parallel processor memory 1622 asin FIG. 16) via a memory interface 1928, which may be an instance of thememory interface 1618 of FIG. 16.

In one embodiment the data assembler 1902 is a processing unit thatcollects vertex data for surfaces and primitives. The data assembler1902 then outputs the vertex data, including the vertex attributes, tothe vertex processing unit 1904. The vertex processing unit 1904 is aprogrammable execution unit that executes vertex shader programs,lighting and transforming vertex data as specified by the vertex shaderprograms. The vertex processing unit 1904 reads data that is stored incache, local or system memory for use in processing the vertex data andmay be programmed to transform the vertex data from an object-basedcoordinate representation to a world space coordinate space or anormalized device coordinate space.

A first instance of a primitive assembler 1906 receives vertexattributes from the vertex processing unit 190. The primitive assembler1906 readings stored vertex attributes as needed and constructs graphicsprimitives for processing by tessellation control processing unit 1908.The graphics primitives include triangles, line segments, points,patches, and so forth, as supported by various graphics processingapplication programming interfaces (APIs).

The tessellation control processing unit 1908 treats the input verticesas control points for a geometric patch. The control points aretransformed from an input representation from the patch (e.g., thepatch's bases) to a representation that is suitable for use in surfaceevaluation by the tessellation evaluation processing unit 1912. Thetessellation control processing unit 1908 can also compute tessellationfactors for edges of geometric patches. A tessellation factor applies toa single edge and quantifies a view-dependent level of detail associatedwith the edge. A tessellation unit 1910 is configured to receive thetessellation factors for edges of a patch and to tessellate the patchinto multiple geometric primitives such as line, triangle, orquadrilateral primitives, which are transmitted to a tessellationevaluation processing unit 1912. The tessellation evaluation processingunit 1912 operates on parameterized coordinates of the subdivided patchto generate a surface representation and vertex attributes for eachvertex associated with the geometric primitives.

A second instance of a primitive assembler 1914 receives vertexattributes from the tessellation evaluation processing unit 1912,reading stored vertex attributes as needed, and constructs graphicsprimitives for processing by the geometry processing unit 1916. Thegeometry processing unit 1916 is a programmable execution unit thatexecutes geometry shader programs to transform graphics primitivesreceived from primitive assembler 1914 as specified by the geometryshader programs. In one embodiment the geometry processing unit 1916 isprogrammed to subdivide the graphics primitives into one or more newgraphics primitives and calculate parameters used to rasterize the newgraphics primitives.

In some embodiments the geometry processing unit 1916 can add or deleteelements in the geometry stream. The geometry processing unit 1916outputs the parameters and vertices specifying new graphics primitivesto primitive assembler 1918. The primitive assembler 1918 receives theparameters and vertices from the geometry processing unit 1916 andconstructs graphics primitives for processing by a viewport scale, cull,and clip unit 1920. The geometry processing unit 1916 reads data that isstored in parallel processor memory or system memory for use inprocessing the geometry data. The viewport scale, cull, and clip unit1920 performs clipping, culling, and viewport scaling and outputsprocessed graphics primitives to a rasterizer 1922.

The rasterizer 1922 can perform depth culling and other depth-basedoptimizations. The rasterizer 1922 also performs scan conversion on thenew graphics primitives to generate fragments and output those fragmentsand associated coverage data to the fragment/pixel processing unit 1924.The fragment/pixel processing unit 1924 is a programmable execution unitthat is configured to execute fragment shader programs or pixel shaderprograms. The fragment/pixel processing unit 1924 transforming fragmentsor pixels received from rasterizer 1922, as specified by the fragment orpixel shader programs. For example, the fragment/pixel processing unit1924 may be programmed to perform operations included but not limited totexture mapping, shading, blending, texture correction and perspectivecorrection to produce shaded fragments or pixels that are output to araster operations unit 1926. The fragment/pixel processing unit 1924 canread data that is stored in either the parallel processor memory or thesystem memory for use when processing the fragment data. Fragment orpixel shader programs may be configured to shade at sample, pixel, tile,or other granularities depending on the sampling rate configured for theprocessing units.

The raster operations unit 1926 is a processing unit that performsraster operations including, but not limited to stencil, z test,blending, and the like, and outputs pixel data as processed graphicsdata to be stored in graphics memory (e.g., parallel processor memory1622 as in FIG. 16, and/or system memory 1504 as in FIG. 15, to bedisplayed on the one or more display device(s) 1510 or for furtherprocessing by one of the one or more processor(s) 1502 or parallelprocessor(s) 1512. In some embodiments the raster operations unit 1926is configured to compress z or color data that is written to memory anddecompress z or color data that is read from memory.

Position-Based Rendering Apparatus and Method for Multi-Die/GPU GraphicsProcessing

As mentioned, as graphics processors scale to larger die sizes, it isdesirable to integrate multiple silicon dies into a single cohesive unitcapable of running a single 3D context in order to addressmanufacturability, scalability, and power delivery problems. Doing thisrequires solutions for multiple classes of scalability as well asinterconnect challenges in order to deliver the best performance on asingle 3D application running on multiple dies. Algorithms currently inuse which attempt to address this problem include alternate framerendering (AFR) and split frame rendering (SFR) as well as variants ofthese approaches.

Existing solutions are limited in terms of performance scaling. Withperfect scaling, a “2-way” (2 GPU) solution would yield 200% performanceover a 1 GPU solution, and a “4-way” (4 GPU) solution would yield 400%performance of a 1 GPU solution. In practice, however, they deliversignificantly lower performance than this.

Detailed measurements for different systems are shown in FIG. 20. Thereare several causes of the scaling limitations. First, geometry work doesnot scale because it must be replicated to all participants in splitframe rendering (SFR) approaches. In addition, cross frame dependenciesrequire copying data between GPUs and hot spotting of work followed bysynchronization points results in waiting threads. Finally, alternateframe rendering (AFR) based approaches induce significant additionallatency. For each GPU included in an AFR chain, the game state todisplay latency increases by one frame. This is untenable for virtualreality/augmented reality (VR/AR) implementations, and undesirable forfast paced gameplay.

One embodiment of the invention utilizes a multi-die and/or multi-GPUarrangement to build a graphics processor capable of delivering scaledup performance on a single 3D application. Tile-based work isintelligently allocated to each die/GPU by monitoring load and usingsynchronization techniques.

The issue with synchronization points is depicted in FIG. 21. In thisdiagram, work partitioned across 4 tiles which starts at time to is notevenly distributed. However, since this work phase requires all work tobe completed before the subsequent work to begin, tiles 0, 2, and 3become idle waiting for tile 1 to complete its work for the phase attime ti.

One embodiment of the invention delivers improved performance scaling ofa 3D workload on multiple graphics processors using the followingimplementations. First, draws are partitioned and sent to individualgraphics dies/GPUs which then execute position-only shaders to determinefull frame visibility data for the draws for all dies. In oneembodiment, the position-only shaders are implemented as shader kernelsexecuted on one or more execution units. In an alternate embodiment,fixed function hardware may be used to calculate the position data.Regardless of the specific implementation, the visibility data indicateswhether a given primitive is present on each of a pre-defined set ofscreen space tiles, collectively referred to herein as a “checkerboard.”

Calculated visibility data for every draw is then sent to the die/GPUthat owns each relevant tile of the checkerboard. Upon receivingrelevant visibility data, each graphics die uses the visibility data tolimit geometry work to only relevant primitives (i.e., those that arevisible), and subsequently performs pixel processing work for all of thetiles of the checkerboard that it owns.

Thus, this embodiment of the invention integrates tile-basedcheckerboard rendering with distributed vertex position calculation toenable more efficient scaling on multi-die GPUs. This approach allowsgeometry work to be partitioned effectively across multiple dies/GPUs,which is a critical failing of existing techniques. Using theembodiments described herein, multi-die GPUs can deliver scaled upperformance as more dies are added without facing the performancelimitations of existing multi-die solutions.

Throughout the following description, a 4-GPU/tile solution is used foran example embodiment. However, it will be appreciated that theunderlying principles of the invention may be extended to any number ofGPUs.

A method in accordance with one embodiment of the invention isillustrated in FIG. 22. The method may be implemented within the contextof the system architectures described above, but is not limited to anyparticular system architectures.

At 2201, a graphics application submits 3D work to a driver via arendering API. For example, the application may call the API to renderand display an image frame. At 2202, the driver assigns position-onlyshading work to each die/GPU. In one embodiment, the driver implementsload balancing when assigning the shading work to ensure that the workis distributed based on the current workloads of each die/GPU. Forexample, if a first die/GPU does not currently have work and a seconddie/GPU is close to being overloaded, then more of the position-onlyshading work will be assigned to the first die/GPU.

At 2203, position-only shading is performed by each respective die/GPUto determine visibility data for each of the checkerboard tiles. Thevisibility data includes an indication as to whether each primitive isvisible within each respective checkerboard tile, or the visibility datacan indicate whether each primitive is visible on any of a GPU's/die'srespective tiles, but not a specific tile.

At 2204, the visibility data is sent to each die/GPU for those tileswhich the die/GPU is responsible for rendering. Each die/GPU then usesthe visibility data to limit its geometry work to only those primitiveswhich are visible. At 2205, each die/GPU implements rendering pipelinework on visible vertices/primitives for each checkerboard tile it owns.In one embodiment, the rendering pipeline includes a geometry shaderprocess the primitives (e.g., generating zero or more primitives from asingle input primitive) and a pixel shader to compute color and otherattributes on a per-pixel basis.

By way of example, and not limitation, FIG. 23 shows a rendered image2300 subdivided into checkerboard tiles (e.g., tiles T0, T1, T2, andT3). Each pattern corresponds to a region of a render target that isassigned to an individual GPU. The dotted pattern tiles (e.g., T0) areassigned to GPU 0, the non-patterned tiles (e.g., T1) are assigned toGPU 1, the tiles with downward sloping lines (e.g., T2) are assigned toGPU 2, and the tiles with checkerboard patterns (e.g., T3) are assignedto GPU 3. As mentioned, each GPU is responsible for generating thecontent of the tiles it owns in accordance with this pattern.

The limitation with the existing solution alone is that each GPU mustperform all geometry work (vertex fetch, vertex shading, clipping,culling, rasterization). This is because the position of a vertex is notknown until after the geometry processing work is complete. Therefore,in the classic checkerboard rendering approach, each GPU must performthe geometry work for every incoming vertex that is drawn across theentire scene—not just the vertices that land on the tiles it owns.

The addition of distributed position shading in the embodiments of theinvention described herein addresses exactly this problem. FIG. 24illustrates the operation of one embodiment in which vertex data 2400 isprocessed by four position-only shaders 2401-2404. In one embodiment,the driver first assigns individual draw calls 2410 from theapplication, illustrated as Draws 0-7, to individual die/GPUs on whichthe POSH shaders 2401-2404 are executed. In alternate embodiments, moreadvanced scheduling can be performed such as vertex count-basedscheduling and GPU idleness-based scheduling to balance the load at alower granularity. In the illustrated example, the draws are assigned(e.g., in a round robin schedule), with draws 0 and 4 being assigned toGPU 2131, draws 1 and 5 assigned to GPU 2132, draws 2 and 6 assigned toGPU 2133, and draws 3 and 7 assigned to GPU 2134.

GPU 2131 will then calculate the position data for draw 0. In doing soit generates visibility data for the vertices contained in that draw forall or a subset of the tiles, which it then communicates to all otherdie/GPUs 2132-2134. The tiles containing visibility data are shown onthe right of the diagram and labelled A0, A4, . . . B0, B4 . . . , C0,C4 . . . , and D0, D4 . . . . This visibility data indicates whethereach vertex is visible on that tile. Thus, the POSH pipelines 2401-2404of this embodiment generate multiple visibility streams, one for eachtile. Once generated, the visibility data is passed to the full renderpipe of each die/GPU 2131-2134. In one embodiment, the visibility datais passed over a point-to-point inter-die/GPU interconnect such asNVLink or PCI express (PCIe).

As illustrated in FIG. 25, each die/GPU 2131-2134 consumes thevisibility data along with the draws submitted by the application.During this rendering pass, the geometry processing 2501-2504 of eachdie/GPU 2131-2134 only processes vertices that are actually visible ontiles within the checkerboard which it owns, filtering out irrelevantvertices using the pre-calculated and shared visibility data 2410. Thegeometry processing 2501-2504 may include, but is not limited to, vertexfetching, vertex shading, hull shading, tessellation, domain shading,rasterization, depth test, and geometry shading. In one embodiment, thegeometry shader of GPU 2131 only processes vertices visible on tilesA0-A4 . . . , but no vertices that are visible on tiles B0-4, C0-4, andD0-4. Similarly, geometry shader within geometry processing 2502 of GPU2132 only processes vertices visible on tiles B0-4, the geometry shaderwithin geometry processing 2503 of GPU 2133 only processes verticesvisible on tiles C0-4, and the geometry shader of the geometryprocessing 2504 of GPU 2134 only processes vertices visible on tilesD0-4.

Pixel processing circuitry/logic 2511-2514 of each die/GPU 2131-2134performs shading operations on the pixels in each respective set oftiles (following rasterization). The resulting sets of tiles are thenmerged in a frame buffer 2550 and rendered on a display (not shown).

In one embodiment, the graphics driver and/or associated circuitryidentifies which draws are assigned to which die/GPUs for geometryprocessing using a per-command die/GPU affinity mask comprising draw-GPUmappings. The driver and/or circuitry may thereby specify thecheckerboard tile pattern to be used and the tile size with the affinitymask. In one embodiment, the visibility vertex data 2410 is generated bythe position-only shader circuitry for all tiles per vertexsimultaneously. In an alternate embodiment, a compute shader is used toperform the visibility calculations and generate per-tile visibilitybuffers rather than dedicated hardware.

Embodiments of the invention may include various steps, which have beendescribed above. The steps may be embodied in machine-executableinstructions which may be used to cause a general-purpose orspecial-purpose processor to perform the steps. Alternatively, thesesteps may be performed by specific hardware components that containhardwired logic for performing the steps, or by any combination ofprogrammed computer components and custom hardware components.

As described herein, instructions may refer to specific configurationsof hardware such as application specific integrated circuits (ASICs)configured to perform certain operations or having a predeterminedfunctionality or software instructions stored in memory embodied in anon-transitory computer readable medium. Thus, the techniques shown inthe figures can be implemented using code and data stored and executedon one or more electronic devices (e.g., an end station, a networkelement, etc.). Such electronic devices store and communicate(internally and/or with other electronic devices over a network) codeand data using computer machine-readable media, such as non-transitorycomputer machine-readable storage media (e.g., magnetic disks; opticaldisks; random access memory; read only memory; flash memory devices;phase-change memory) and transitory computer machine-readablecommunication media (e.g., electrical, optical, acoustical or other formof propagated signals—such as carrier waves, infrared signals, digitalsignals, etc.).

In addition, such electronic devices typically include a set of one ormore processors coupled to one or more other components, such as one ormore storage devices (non-transitory machine-readable storage media),user input/output devices (e.g., a keyboard, a touchscreen, and/or adisplay), and network connections. The coupling of the set of processorsand other components is typically through one or more busses and bridges(also termed as bus controllers). The storage device and signalscarrying the network traffic respectively represent one or moremachine-readable storage media and machine-readable communication media.Thus, the storage device of a given electronic device typically storescode and/or data for execution on the set of one or more processors ofthat electronic device. Of course, one or more parts of an embodiment ofthe invention may be implemented using different combinations ofsoftware, firmware, and/or hardware. Throughout this detaileddescription, for the purposes of explanation, numerous specific detailswere set forth in order to provide a thorough understanding of thepresent invention. It will be apparent, however, to one skilled in theart that the invention may be practiced without some of these specificdetails. In certain instances, well known structures and functions werenot described in elaborate detail in order to avoid obscuring thesubject matter of the present invention. Accordingly, the scope andspirit of the invention should be judged in terms of the claims whichfollow.

What is claimed is:
 1. A method comprising: dividing an image frame intoa plurality of tiles; assigning a non-overlapping subset of the tiles toeach of a plurality of graphics processors, wherein each of the graphicsprocessors is integrated on a separate semiconductor die and comprises agraphics pipeline for rendering the assigned subset of tiles;distributing a plurality of graphics draws to the plurality of graphicsprocessors, wherein each of the graphics processors is assigned a subsetof the plurality of graphics draws; performing position-only shading ateach of the graphics processors using vertex data associated with thesubset of graphics draws assigned to the graphics processor to generatevertex visibility data for each of the plurality of tiles; distributingdifferent subsets of the vertex visibility data to different graphicsprocessors located on different semiconductor dies, wherein each of thegraphics processers is to receive a subset of the vertex visibility datafor the tiles on which the graphic processor is to perform geometrywork; limiting geometry work to be performed on the tiles assigned toeach graphics processor using the subset of the vertex visibility datareceived by each of the graphics processors; rendering the assignedsubset of tiles at each graphics processor to generate rendered tiles;and combining the rendered tiles to generate a complete image frame. 2.The method of claim 1, wherein the vertex visibility data generated ateach graphics processor comprises an indication of whether eachprimitive associated with the graphics draws assigned the graphicsprocessor is visible within each of the plurality of tiles.
 3. Themethod of claim 1, wherein the vertex visibility data generated at eachgraphics processor comprises an indication of whether each primitiveassociated with the graphics draws assigned to the graphics processor isvisible within any of the tiles assigned to the processor but not of aspecific tile.
 4. The method of claim 1, wherein the vertex visibilitydata is generated via position-only shading for all tiles per vertexsimultaneously.
 5. The method of claim 1, wherein the plurality ofgraphics draws is distributed to the plurality of graphics processorsbased on a vertex count-based scheduling scheme.
 6. The method of claim1, wherein the plurality of graphics draws is distributed to theplurality of graphics processors based on a graphics processoridleness-based scheduling scheme.
 7. The method of claim 1, wherein theplurality of graphics draws is distributed to the plurality of graphicsprocessors based on a round robin scheduling scheme.
 8. The method ofclaim 1, wherein the vertex visibility data generated at each graphicsprocessor is distributed to all other graphics processors.
 9. The methodof claim 1, wherein the vertex visibility data generated at eachgraphics processor is distributed to a subset of the other graphicsprocessors.
 10. The method of claim 1, wherein the vertex visibilitydata generated at each graphics processor is distributed to othergraphics processors via point-to-point inter-die interconnects.
 11. Themethod of claim 1, wherein performing position-only shading comprises:comparing primitives included in the vertex data for each tile toidentify one or more primitives which are visible within each tile'sregion; and identifying occluded primitives in the vertex data.
 12. Themethod of claim 11, wherein limiting geometry work processing comprisesperforming geometry work using only those primitives which are visible.13. The method of claim 12 further comprising: rasterizing the subsetsof tiles by each respective graphics processor to generate pixels foreach tile of each subset of tiles.
 14. A graphics processing systemcomprising: a plurality of graphics processors, each graphics processorassigned a non-overlapping subset of a plurality of tiles of an imageframe, wherein each of the graphics processors is integrated on aseparate semiconductor die and comprises a graphics pipeline forrendering the assigned subset of tiles; a graphics driver to assign aplurality of graphics draws to the plurality of graphics processors,wherein each of the graphics processors is assigned a subset of theplurality of graphics draws; each of the plurality of graphicsprocessors to perform position-only shading using vertex data associatedwith the subset of graphics draws assigned to the graphics processor togenerate vertex visibility data for each of the plurality of tiles; eachof the plurality of graphics processors further to distribute differentsubsets of the vertex visibility data to different graphics processorslocated on different semiconductor dies, wherein each of the graphicsprocessers is to receive a subset of the vertex visibility data for thetiles on which to perform geometry work; geometry shaders of each of theplurality of graphics processors to process primitives of a respectivesubset of tiles, the geometry shader to read the vertex visibility datareceived by the graphics processor to limit geometry work to beperformed each of the graphics processors to responsively generaterendered tiles; and wherein the rendered tiles are to be combined togenerate a complete image frame.
 15. The graphics processing system ofclaim 14, wherein the vertex visibility data generated at each graphicsprocessor comprises an indication of whether each primitive associatedwith the graphics draws assigned the graphics processor is visiblewithin each of the plurality of tiles.
 16. The graphics processingsystem of claim 14, wherein the vertex visibility data generated at eachgraphics processor comprises an indication of whether each primitiveassociated with the graphics draws assigned to the graphics processor isvisible within any of the tiles assigned to the processor but not of aspecific tile.
 17. The graphics processing system of claim 14, whereinthe vertex visibility data is generated via position-only shading forall tiles per vertex simultaneously.
 18. The graphics processing systemof claim 14, wherein the plurality of graphics draws is distributed tothe plurality of graphics processors based on a vertex count-basedscheduling scheme, a graphics processor idleness-based schedulingscheme, or a round robin scheduling scheme.
 19. The graphics processingsystem of claim 14, wherein the vertex visibility data generated at eachgraphics processor is distributed to all other graphics processors. 20.The graphics processing system of claim 14, wherein the vertexvisibility data generated at each graphics processor is distributed to asubset of the other graphics processors.
 21. The graphics processingsystem of claim 14, wherein the vertex visibility data generated at eachgraphics processor is distributed to other graphics processors viapoint-to-point inter-die interconnects.
 22. The graphics processingsystem of claim 14, wherein each of the plurality of graphics processorsis further to compare primitives included in the vertex data for eachtile to identify one or more primitives which are visible within eachtile's region and to identify occluded primitives in the vertex data.23. The graphics processing system of claim 22, wherein the geometryshader is to limit geometry work to be performed by performing geometrywork using only those primitives which are visible.
 24. The graphicsprocessing system of claim 23, wherein each of the plurality of graphicsprocessors is further to rasterize the subset of tiles assigned to thegraphics processor to generate pixels for each of the tiles in theassigned subset.